LTC2421 datasheet(30/32 Pages) LINER

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LTC2421/LTC2422

24212f

APPLICATIO S I FOR ATIO

SCK

SDO

GND

VCC

FSSET

CH1

CH0

ZSSET

LTC2422

24212 F36

LT1761-5

GND

µF

10V

TANT

µF

10V

TANT

µF

16V

TANT

µF

10V

TANT

µF

1/2 BAT54C

ISOLATION

BARRIER

= LOGIC COMMON

= FLOATING COMMON

T1 = COILTRONICS CTX02-14659

OR SIEMENS B78304-A1477-A3

µF

CERAMIC

VCC2

ST2

VCC1

ST1

“SDO”

“SCK”

LOGIC 5V

OUT

SHDN

BYP

LTC1535

Figure 36. Complete, Isolated 20-Bit Data Acquisition System

Below 4.2V, the LTC1535’s driver outputs Y and Z are in a

high impedance state, allowing the 1k

Ω pull-down to de-

fine the logic state at SCK. When the LTC2422 first be-

comes active, it samples SCK; a logic “0” provided by the

Ω pull-down invokes the external serial clock mode. In

this mode, the LTC2422 is controlled by a single clock line

from the nonisolated side of the barrier, through the

LTC1535’s driver output Y. The entire power-up sequence,

from the time power is applied to VCC1 until the LT1761’s

output has reached 5V, is approximately 1ms.

Data returns to the nonisolated side through the LTC1535’s

receiver at RO. An internal divider on receiver input B sets

a logic threshold of approximately 3.4V at input A, facili-

tating communications with the LTC2422’s SDO output

without the need for any external components.

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