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EP224 Datasheet(PDF) 14 Page - Altera Corporation

Part # EP224
Description  Classic EPLDs
PDF  16 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP224 Datasheet(HTML) 14 Page - Altera Corporation

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Altera Corporation
EP220 & EP224 Classic EPLDs
AC Operating Conditions: -7 & -10 Speed Grades
Note (1)
Notes to tables:
(1)
Operating conditions: VCC = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
(2)
Measured with three I/O outputs switching.
(3)
The tPZX and tPXZ parameters are measured at ± 0.5 V from steady-state voltage that is driven by the specified
output load. The tPXZ parameter is measured with CL = 5 pF and with all eight outputs switching.
Combinatorial Mode
EP220-7
EP224-7
EP220-10
EP224-10
Symbol
Parameter
Min
Max
Min
Max
Units
tPD1
Input or I/O to non-registered output, inversion on,
Note (2)
7.5
10
ns
tPD2
Input or I/O to non-registered output, inversion off,
Note (2)
8.5
10
ns
tPZX
Input or I/O to output enable,
Note (3)
910
ns
tPXZ
Input or I/O to output disable,
Note (3)
910
ns
tOSR
Register mode output-to-output skew
300
300
ps
tOSC
Combinatorial mode output-to-output skew
400
400
ps
Synchronous Clock Mode
EP220-7
EP224-7
EP220-10
EP224-10
Symbol
Parameter
Min
Max
Min
Max
Units
fMAX
Maximum frequency (pipelined), no feedback,
Note (2)
100
62.5
MHz
fCNT1
Maximum counter frequency, external feedback,
Note (2)
74
58.8
MHz
fCNT2
Maximum counter frequency, internal feedback,
Note (2)
100
60.6
MHz
tSU1
Input or I/O setup time to global clock
7
10
ns
tH
Input or I/O hold time from global clock
0
0
ns
tCO1
Global clock to output delay,
Note (2)
6.5
7
ns
tCO2
Global clock to output delay through combinatorial macrocell
11
13
ns
tCNT
Minimum global clock period,
Note (2)
10
16.5
ns
tCL
Clock low time
4
7
ns
tCH
Clock high time
4
7
ns
tCP
Clock period
10
16
ns



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