DP83955AV datasheet(34/54 Pages) NSC

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50 Functional Description (Continued)

74LS259 Latch Inputs

259 Output

259 Addr S(2 – 0)

000

001

010

011

100

101

110

111

LERIC Port Number

1 (AUI)

LERIC D0

ACOL

LINK

LERIC D1

AREC

COL

LERIC D2

JAB

REC

LERIC D3

APART

PART

LERIC D4

BDPOL

Note

This shows the LED Output Functions for the LED Drivers when 74LS259s are used

ACOL e Any Port Collision AREC e Any Port Reception JAB e Any Port Jabbering

LINK e Port Link COL e Port Collision REC e Port Reception PART e Port Partitioned

BDPOL e Bad (inverse) Polarity of received data

FIGURE 5-10 Maximum Mode LED Definitions

Description of Data Freeze Strobe (DFS) Pin Operation

DFS has been implemented to assist the user to provide

partial hub management statistics on a per packet per port

basis The DFS signal is asserted active high at the end of

the transmission of each packet and the status of that

packet is frozen on the LEDs until the beginning of the next

received packet or for a maximum of 30 ms as is shown in

Figure 5-11

The DFS signal can be used to latch the LED information

into a shared buffer which acts as an external flag register

and can be used as a mechanism to trap events

TLF11240 – 41

FIGURE 5-11 DFS Operation

Processor Access Cycles

Access to the LERIC’s on-chip registers is made via its

processor interface This utilizes a conventional non-multi-

plexed address (four bit) and data (four bit) bus This bus is

also used to provide data and address information to off

chip LED display latches during display update cycles While

performing these cycles the LERIC behaves as a master of

its data bus Consequently a TRI-STATE bi-directional bus

transceiver (eg

74LS245) must be placed between the

LERIC and any processor bus

Internally each of the

LERIC’s registers is 8 bits however there are four bits of

data pins (D(30)) Each register is accessed on a nibble

basis (4 bits at a time) D(7) of the address pins D(74) se-

lects the upper and lower nibbles as described in Section 7

To access the LERIC’s registers the processor requests a

input strobes The LERIC responds by finishing any current

display update cycle and asserts the TRI-STATE buffer en-

able signal (BUFEN) If the processor cycle is a write cycle

then the LERIC’s buffers are disabled to prevent contention

In order to interface to the LERIC a PAL device may be

used to perform the following operations

1 Generate the LERIC’s read and write strobes

2 Control the direction signal for the 74LS245

An example of the processor and display interfaces is

shown in

Figure 5-12

DP83955AV Datasheet(PDF) 34 Page - National Semiconductor (TI)

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