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DP83955AV Datasheet(PDF) 39 Page - National Semiconductor (TI) |
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DP83955AV Datasheet(HTML) 39 Page - National Semiconductor (TI) |
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39 / 54 page  70 LERIC Registers 71 LERIC REGISTER ADDRESS MAP The LERIC’s registers may be accessed by applying the required address to the four register address (D(74)) input pins Pin D(7) makes the selection between the upper and lower nibbles of each register The register map consists of 8 registers as shown in the Register Map in Table 7-1 which is followed by a summary of the register bits shown in Table 7-2 The definitions for these bits are shown in the detailed register definitions on the following pages TABLE 7-1 Register Memory Map Address D(74) Name 0000 LERIC Status RegisterLower Nibble 1000 LERIC Status RegisterUpper Nibble 0001 Port 1 Status and Configuration RegisterLower Nibble 1001 Port 1 Status and Configuration RegisterUpper Nibble 0010 Port 2 Status and Configuration RegisterLower Nibble 1010 Port 2 Status and Configuration RegisterUpper Nibble 0011 Port 3 Status and Configuration RegisterLower Nibble 1011 Port 3 Status and Configuration RegisterUpper Nibble 0100 Port 4 Status and Configuration RegisterLower Nibble 1100 Port 4 Status and Configuration RegisterUpper Nibble 0101 Port 5 Status and Configuration RegisterLower Nibble 1101 Port 5 Status and Configuration RegisterUpper Nibble 0110 Port 6 Status and Configuration RegisterLower Nibble 1110 Port 6 Status and Configuration RegisterUpper Nibble 0111 Port 7 Status and Configuration RegisterLower Nibble 1111 Port 7 Status and Configuration RegisterUpper Nibble Register Array Bit Map Address D(74) D(3) D(2) D(1) D(0) 0000 PART JAB AREC ACOL 1000 Resv Resv Resv Resv 0001 PART REC COL GDLNK 1001 DISPT Resv Resv Resv 0010 PART REC COL GDLNK 1010 DISPT Resv POL SQRL 0011 PART REC COL GDLNK 1011 DISPT Resv POL SQL 0100 PART REC COL GDLNK 1100 DISPT Resv POL SQL 0101 PART REC COL GDLNK 1101 DISPT Resv POL SQL 0110 PART REC COL GDLNK 1110 DISPT Resv POL SQL 0111 PART REC COL GDLNK 1111 DISPT Resv POL SQL 39 |
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