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DP83955AV Datasheet(PDF) 49 Page - National Semiconductor (TI) |
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DP83955AV Datasheet(HTML) 49 Page - National Semiconductor (TI) |
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49 / 54 page  100 Switching Characteristics (Continued) REGISTER READ TIMING TLF11240 – 32 Symbol Number Parameter Min Max Units rdadrs T80 Address Setup from BUFEN Low 0 85 ns rdadrh T81 Address Hold after RD High 0 ns rdlbufl T82 RD Low to BUFEN Low 80 355 ns rdhbufh T83 RD High to BUFEN High 35 ns bufldatv T84 BUFEN Low to Data Valid 190 ns rddath T85 Read Data Hold 60 ns rdw T88 RD Width 650 ns rdtr T89 RD Low to D(74) TRI-STATE 80 355 ns Note Minimum high time between readwrite cycles is 100 ns REGISTER WRITE TIMING TLF11240 – 33 Symbol Number Parameter Min Max Units wradrs T90 Address Setup from BUFEN Low 0 14 ns wradrh T91 Address Hold after WR High 0 ns wrlbufl T92 WR Low to BUFEN Low 80 355 ns wrhbufh T93 WR High to BUFEN High 35 ns wradatv T94 BUFEN Low to Data Valid 160 ns wrdath T95 Write Data Hold 0 ns wrdatr T96 BUFEN Low to Data Latched 245 ns wrw T98 WR Width 650 ns wrtr T99 WR Low to D(70) TRI-STATE 80 355 ns Note Minimum high time between readwrite cycles is 100 ns 49 |
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