MP1230A/31A/32A

5

Rev. 2.00

TIMING DIAGRAM

50%

50%

50%

50%

50%

50%

SETTLED TO

+0.01%

CS, BYTE1/BYTE2

WR

DATA BITS

DEFINITION OF CONTROL SIGNALS:

CS:

Chip Select.(Active low)

It will enable WR1.

WR1:

Write 1 (Active low)

The WR1 is used to load the digital data bits (DB) into

the input latch.

BYTE1/BYTE2:

Byte sequence control.

The BYTE1/BYTE2 control pin is used to select both

MSB and LSB input latches.

WR2:

Write 2 (Active low)

It will enable XFER.

XFER:

Transfer control signal (Active low)

This signal in combination with WR2 causes the 16-bit

data which is available in the input latches to transfer

to the DAC register

DB0 to DB11: Digital Inputs.

DB0 is the least significant digital input (LSB) and

DB11 is the most significant digital input (MSB).

DAC Current Output 1 Bus.

DAC register, and is zero for all 0’s in the DAC register.

DAC Current Output 2 Bus.

Feedback Resistor.

This internal feedback resistor should always be used

(not an external resistor) since it matches the resistors

in the DAC and tracks these resistors over tempera-

ture.

Reference Voltage Input.

This input connects an external precision voltage

over the range of +25V to –25V or the analog signal for

a 4-quadrant multiplying mode application.

Power Supply Voltage.

be from +5 V DC to +15 V DC, however optimum volt-

age is +12 to +15 V DC.

AGND: Analog Ground

Back gate of the DAC N-channel current steering

switches.

DGND: Digital Ground