MP1230A/31A/32A

1

Rev. 2.00

FEATURES

• Superior Ruggedized 1230 Series: 2 KV ESD

• Four Quadrant Multiplication

• Stable, More Accurate Segmented DAC Approach

–

0.2 ppm/

°C Linearity Tempco

–

2 ppm/

°C Max Gain Error Tempco

–

Lowest Sensitivity to Amplifier Offset

–

–

Lower Glitch Energy

• Monotonic over Temperature Range

CMOS Microprocessor Compatible

Double-Buffered 12-Bit

Digital-to-Analog Converter

• Lower Data Bus Feedthrough @ CS = 1

• Latch-Up Free CMOS Technology

• 12-Bit Bus Version: MP1208/1209/1210

• 16-Bit Upgrade: MP7636A

GENERAL DESCRIPTION

The MP1230A series are superior pin for pin replacements

for the 1230 series. The MP1230A series is manufactured using

advanced thin film resistors on a double metal CMOS process

which promotes significant improvements in reliability, latch-up

free performance and ESD protection.

The MP1230A series incorporates a unique decoding tech-

nique yielding lower glitch, higher speed and excellent accuracy

over temperature and time. 12-bit linearity is achieved without

trimming. Outstanding features include:

–

Stability: integral and differential linearity tempcos are rated

at 0.2 ppm/

temperature ranges. Scale factor tempco is a low 2 ppm/

maximum.

–

Low Output Capacitance: Due to smaller MOSFET switch

geometries allowed by decoding, the output capacitance at

less than half the competitive DAC 1230 series. Lower ca-

pacitance allows the MP1230A series to achieve settling

times faster than 1

–

Low Sensitivity to Output Amplifier Offset: The linearity er-

ror caused by amplifier offset is reduced by a factor of 2 in the

MP1230A series over conventional R-2R DACs.

The MP1230A series uses a circuit which reduces transients

in the supplies caused by DATA bus transitions at CS = 1.

SIMPLIFIED BLOCK DIAGRAM

DGND

12

DQ

DQ

DB11-DB4

DB3-DB0

DQ

AGND

12

8

4

4

8

8

INPUT LATCH

DAC LATCH

BYTE1/BYTE2

CS

WR1

XFER WR2

LE

LE

LE