LT8610 datasheet(14/28 Pages) LINER

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LTC3646/LTC3646-1

36461fc

For more information www.linear.com/LTC3646

Figure 2. Optional Feedforward Capacitor

VFB

3646 F02

VOUT

SGND

LTC3646

APPLICATIONS INFORMATION

The design example on the back page uses a DFLS1200

based on its low reverse leakage over the voltage and

temperature ratings of the LTC3646.

Output Voltage Programming

The LTC3646 will adjust the output voltage such that VFB

equals the reference voltage of 0.6V according to:

VOUT = 0.6V 1+













The desired output voltage is set by the appropriate selec-

tion of resistors R1 and R2 as shown in Figure 2. Choosing

largevaluesforR1andR2willresultinimprovedefficiency

but may lead to undesired noise coupling or phase margin

reduction due to stray capacitance at the VFB node. Care

should be taken to route the FB line away from any noise

source, such as the SW line.

Whenprogrammingoutputvoltagesabove 12V,aSchottky

diode connected between BOOST and INTVCC is needed

(see the Boost Capacitor and Diode section.)

To improve the frequency response of the main control

loop a feedforward capacitor, CF, may be used as shown

in Figure 2.

Minimum Off-Time/On-Time Considerations

The minimum off-time is the smallest amount of time that

the LTC3646 can turn on the bottom power MOSFET, trip

the current comparator and turn off the power MOSFET.

This time is typically 80ns. For the controlled on-time

current mode control architecture, the minimum off-time

limit imposes a maximum duty cycle of:

DC(MAX) = 1 – (fO • tOFF(MIN))

where fO is the switching frequency and tOFF(MIN) is the

minimumoff-time.Ifthemaximumdutycycleissurpassed,

due to a dropping input voltage for example, the output

will drop out of regulation. The minimum input voltage to

avoid this dropout condition is:

VIN(MIN) =

VOUT

1− fO • tOFF(MIN)

(

)

If there is concern about operating near the minimum

off-time limits, consider reducing the frequency to add

margin to the design.

Conversely, the minimum on-time is the smallest dura-

tion of time in which the top power MOSFET can be in

its “on” state. This time is typically 30ns. In continuous

mode operation, the minimum on-time limit imposes a

minimum duty cycle of:

DC(MIN) = (fO • tON(MIN))

where tON(MIN) is the minimum on-time. As the equation

shows, reducing the operating frequency will alleviate the

minimumdutycycleconstraint.Intherarecaseswherethe

minimum duty cycle is surpassed, the output voltage will

still remain in regulation, but the switching frequency will

decreasefromitsprogrammedvalue.Thisisanacceptable

result in many applications, so this constraint may not be

of critical importance in some cases, and high switching

frequencies may be used in the design without any fear

of severe consequences. As the sections on Inductor and

CapacitorSelectionshow,highswitchingfrequenciesallow

the use of smaller board components, thus reducing the

footprint of the application circuit.

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