signal (error amplifier output) to be

∼0.7 V greater than the voltage across CT to inhibit the output logic, and

ensures maximum duty cycle operation without requiring the control voltage to sink to a true ground potential.

The output pulse width varies from 97% of the period to 0 as the voltage present at the error amplifier output

varies from 0.5 V to 3.5 V, respectively.

9.3.6 Error Amplifiers

Both high-gain error amplifiers receive their bias from the VI supply rail. This permits a common-mode input

voltage range from –0.3 V to 2 V less than VI. Both amplifiers behave characteristically of a single-ended

single-supply amplifier, in that each output is active high only. This allows each amplifier to pull up independently

for a decreasing output pulse-width demand. With both outputs ORed together at the inverting input node of the

PWM comparator, the amplifier demanding the minimum pulse out dominates. The amplifier outputs are biased

low by a current sink to provide maximum pulse width out when both amplifiers are biased off.

9.3.7 Output-Control Input

The output-control input determines whether the output transistors operate in parallel or push-pull. This input

is the supply source for the pulse-steering flip-flop. The output-control input is asynchronous and has direct

control over the output, independent of the oscillator or pulse-steering flip-flop. The input condition is intended

to be a fixed condition that is defined by the application. For parallel operation, the output-control input must

be grounded. This disables the pulse-steering flip-flop and inhibits its outputs. In this mode, the pulses seen at

the output of the dead-time control/PWM comparator are transmitted by both output transistors in parallel. For

push-pull operation, the output-control input must be connected to the internal 5-V reference regulator. Under

this condition, each of the output transistors is enabled, alternately, by the pulse-steering flip-flop.

9.3.8 Output Transistors

Two output transistors are available on the TL494. Both transistors are configured as open collector/open

emitter, and each is capable of sinking or sourcing up to 200 mA. The transistors have a saturation voltage of

less than 1.3 V in the common-emitter configuration and less than 2.5 V in the emitter-follower configuration.

The outputs are protected against excessive power dissipation to prevent damage, but do not employ sufficient

current limiting to allow them to be operated as current-source outputs.

9.4 Device Functional Modes

When the OUTPUT CTRL pin is tied to ground, the TL494 is operating in single-ended or parallel mode. When

the OUTPUT CTRL pin is tied to VREF, the TL494 is operating in normal push-pull operation.

TL494

SLVS074I – JANUARY 1983 – REVISED JULY 2022

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