DS3131DK

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1. GENERAL OVERVIEW

The DS3131DK is a demonstration and evaluation kit for the DS3131 BoSS bit-synchronous HDLC

controllers. The DS3131DK is intended to be used in a full-size PC platform, complete with PCI. The

platform must be at least a 200MHz+ Pentium II class CPU with 32MB of RAM. Figure 1-1 details an

outline of the PCI board for the DS3131DK.

The DS3131DK was designed to be as simple as possible but provides the flexibility to be used in a

number of different configurations. The DS3131DK has all of the port pins and the local bus pins from

the DS3131 that are easily accessible through headers on top of the card. A second DS3131DK can also

be loaded into the PC in an adjacent PCI slot to add additional functions such as:

§ Multiple T1/E1 framers

§ T3 line interface

§ HSSI interface

§ V.35 interfaces

An Altera 9000 series PLD device is connected to all of the port pins on the DS3131. The PLD is capable

of being loaded with various configurations through a programming port (J4) that resides on the

DS3131DK. This PLD generates clocks and frame syncs as well as routes data from one port to another

in a daisy-chain fashion to allow testing the device under worst-case loading (Figure 1-2). Two

oscillators provide the port timing.

The transmit side of a port is derived from one clock and the receive side from another, so that they can

be asynchronous to one another. If the PLD is not needed, it can be three-stated to remove it (electrically)

from the board. Signals can then be sent to the DS3131 by the pin headers.

The board is intended to be a full-size PCI card that can only be plugged into a 5V PCI system

environment. There is a 256-pin plastic BGA socket on the board for the DS3131.

Only the DS3131 is operated at 3.3V. Since it cannot be guaranteed that a 3.3V supply exists in a 5V PCI

system environment, the DS3131DK has a linear regulator on it (U4: LT1086) to convert from 5V to

3.3V. All of the other logic, including the PLD and oscillators, operate at 5V. If 3.3V exists on the PCI

bus, the linear regulator can be removed and a 0Ω jumper can be installed at R97 (Figure 1-1).

The JTAG pins on the DS3131 are not active on the DS3131DK. Therefore, the JTCLK, JTDI, and JTMS

signals are wired to 3.3V and JTRST is wired low.

The DS3131DK was designed to use the device’s 28-port mode rather than the 40-port mode, so the local

bus can be used.

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