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EFP01 Datasheet(PDF) 124 Page - Silicon Laboratories |
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EFP01 Datasheet(HTML) 124 Page - Silicon Laboratories |
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124 / 158 page ![]() 6.2.32 EM_CRSREG_CTRL Offset Bit Position 0x43 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0x00 0 Access Name Table 6.32. EM_CRSREG_CTRL Bit Name Reset Access Description 7 CRSREG_EN_C 0 read-write If set, VOC coarse regulator will be enabled in EM4 mode 6 CRSREG_EN_B 0 read-write If set, VOB coarse regulator will be enabled in EM4 mode 5 CRSREG_EN_A 0 read-write If set, VOA coarse regulator will be enabled in EM4 mode 4 CRSREG_BYP 0 read-write If set, any enabled coarse regulator outputs are shorted to VDDB through an internal switch. 3 FORCE_EM0 0 read-write Force EM0 state on any I2C start condition. Recommend to always set FORCE_EM0=1 when using Direct Mode. Refer to usage notes in the EM_SEL bit description. 2:1 EM_SEL 0x00 read-write Selects energy mode when not using direct mode. Note that this rbit may not accurately reflect the current energy mode state when FORCE_EM0 is set. For example, if FORCE_EM0 =1 and EM_SEL is set to 2, the EFP01 en- ters EM2 mode. If an I2C read/write occurs at that point, the EFP01 automatically enters EM0, but the EM_SEL bit- field is not updated and will still read 2. Firmware can reliably determine the current EFP01 energy mode as shown below: EFP01 Energy Mode = EM_CRSREG_CTRL.FORCE_EM0 ? ‘EM0’ : EM_CRSREG_CTRL.EM_STSEL Value Mode Description 0 EM0 Energy Mode 0 1 RESERVED Reserved 2 EM2 Energy Mode 2 3 EM4 Energy Mode 4 EFP01 Energy Friendly PMIC Family Data Sheet Register Definitions silabs.com | Building a more connected world. Rev. 1.3 | 124 |
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