MAX22196 datasheet(52/61 Pages) AD

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MAX22196

Octal Industrial Sink/Source

Digital Input

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Analog Devices | 52

Applications Information

Power Supply Sequencing

The MAX22196 does not require special power supply sequencing. The logic interface supply (VL) is set independently

from the field supply (V24) or LDO output (VA) levels.

Power Supply Decoupling

To reduce ripple and the chance of introducing data errors, bypass V24 and VA with 1μF ceramic capacitors to GND and

bypass VL with 0.1μF ceramic capacitor to GND, respectively. Place the bypass capacitors as close as possible to the

power supply input pins.

PCB Layout Recommendations

The PCB designer should follow some critical recommendations in order to get the best performance from the design.

• Keep the input/output traces as short as possible. To keep signal paths low-inductance, avoid using vias.

• Have a solid ground plane underneath the entire EP area with multiple thermal vias for best thermal performance.

• Maximize the metal coverage for all layers, especially for top and bottom layer to optimize the heat dissipation.

• Use 2oz copper for top and bottom layer if possible so that more heat can be drawn to the PCB.

• Maximize the number of vias under the package for thermal purposes. If possible, fill the via with copper, which further

enhances the vertical heat transfer through the PCB.

Powering VA Supply Externally

The VA pin can alternatively be powered by an external 3V to 5.5V supply. In this configuration, disable the on-chip

regulator by connecting REGEN pin to GND. This configuration reduces the power dissipation in the chip by 1.3mA x (V24

- 5V), typical. When powering the MAX22196 from an external 3.3V or 5V supply on VA, V24 must be powered by external

24V supply for source configurations. If the MAX22196 is only operated in sink or TTL configurations, V24 can be powered

by the external VA supply, and a 24V supply is not needed.

When V24 is powered by the VA supply, the device always indicates a 24V undervoltage fault due to the V24UV bit in the

FAULT1 register, and the FAULT pin is always active (low) if the bit is unmasked in the F1MASK register. To overcome

this, set bit V24UV_M in the F1MASK register to 1.

Isolating the SPI

A companion digital isolator, the MAX14483, is optimized to support the MAX22196. The MAX14483 is a six-channel,

3.75kVRMS, low-power digital isolator ideal for interfacing to low-voltage products such as microcontrollers or FPGAs.

Figure 18 demonstrates two MAX22196 devices in daisy-chain operation, showing SPI signals, control signals, and power

monitoring signal isolated between the field and logic side of the design. A single MAX14483 can be used for multiple

MAX22196 devices. Figure 19 demonstrates two MAX22196 devices operated in addressable SPI mode, meaning they

share a common chip select (CS) signal from the SPI controller (MCU or FPGA).

The addressable SPI mode can accommodate up to four devices sharing a common CS signal. When more than four

devices are required in a module, daisy-chain configuration can be used. In daisy-chain mode, the number of SPI clock

cycles per read or write command is N x 16 with CRC disabled, or N x 24 with CRC enabled, where N is the number of

devices in the daisy chain, creating a longer SPI read/write delay.

MAX22196 Datasheet(PDF) 52 Page - Analog Devices