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MAX22196 Datasheet(PDF) 13 Page - Analog Devices

Part # MAX22196
Description  Octal Industrial Sink/Source Digital Input
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

MAX22196 Datasheet(HTML) 13 Page - Analog Devices

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MAX22196
Octal Industrial Sink/Source
Digital Input
www.analog.com
Analog Devices | 13
9
FAULT
Active-Low, Low-Side, Open-Drain Fault Indicator. FAULT goes low to
indicate that one or more of the flags in the FAULT registers have been set.
Connect a pullup resistor from FAULT to VL.
VL
Digital
Output
10
READY
Active-Low, High-Side, Open-Drain Output. READY goes low when VA and
VL are both above their respective UVLO thresholds, indicating that the
MAX22196 is powered up and ready for operation. Connect a pulldown
resistor from READY to GND.
VL
Digital
Output
11
LATCH
Both LATCH and CS control data latching at the input of the serializer (after
the inputs). The latch is transparent when both CS and LATCH are high. The
data at the input of the serializer is frozen on the falling edge of either LATCH
or CS. LATCH is typically used to synchronize input channel sampling across
multiple MAX22196 devices. LATCH has a weak internal pullup.
VL
Digital
Input
13
CS
Chip Select Input. Assert low to latch input states and enable the SPI
interface. CS has a weak internal pullup.
VL
Digital
Input
14
SCLK
Serial Clock Input. SCLK has a weak internal pulldown.
VL
Digital
Input
15
SDI
Serial Data Input. Data is clocked into SDI on the rising edge of SCLK. SDI
has a weak internal pulldown.
VL
Digital
Input
16
SDO
Serial Data Output. Data is updated on the falling edge of SCLK. When CS is
high, SDO is high impedance.
VL
Digital
Output
CONFIGURATION PINS
17
CRCEN
CRC Enable Pin. Drive CRCEN pin high to enable CRC generation and error
detection on the SPI interface. Drive CRCEN pin low if CRC is not used.
CRCEN has a weak internal pulldown.
VL
Digital
Input
18
DAISY
Daisy-Chain Enable Pin. Drive DAISY pin high to enable daisy-chained SPI
mode. Drive DAISY pin low if daisy-chain mode is not used. DAISY has a
weak internal pulldown.
VL
Digital
Input
30
REFDI
Digital Input Current-Limit Reference Resistor. For Type 1 and Type 3 inputs,
place a 12kΩ resistor from REFDI to GND. See the Detailed Description
section for details.
VA
Analog
Input
31
A0
Chip Address LSB for Addressable SPI. See Table 4.
VL
Digital
Input
32
A1
Chip Address MSB for Addressable SPI. See Table 4.
VL
Digital
Input
LED MATRIX/GPO OUTPUTS
21
LO4
Channel 4 LED Common Cathode Connection (Open-Drain Low-Side) when
GPO bit in the GLOBLCFG register is 0, or General-Purpose Logic Output 4
(Push-Pull) when GPO bit in the GLOBLCFG register is 1. Connect a resistor
in series when configured as an LED output to set the LED current. Leave
unconnected, if not used. See the LED Matrix section for connection/details.
VA
Digital
Output
20
LO5
Channel 5 LED Common Cathode Connection (Open-Drain Low-Side) when
GPO bit in the GLOBLCFG register is 0, or General-Purpose Logic Output 5
(Push-Pull) when GPO bit in the GLOBLCFG register is 1. Connect a resistor
in series when configured as an LED output to set the LED current. Leave
unconnected, if not used. See the LED Matrix section for connection/details.
VA
Digital
Output
19
LO6
Channel 6 LED Common Cathode Connection (Open-Drain Low-Side) when
GPO bit in the GLOBLCFG register is 0, or General-Purpose Logic Output 6
(Push-Pull) when GPO bit in the GLOBLCFG register is 1. Connect a resistor
in series when configured as an LED output to set the LED current. Leave
unconnected, if not used. See the LED Matrix section for connection/details.
VA
Digital
Output
24
LO1
Channel 1 LED Common Anode Connection (Open-Drain High-Side) when
GPO bit in the GLOBLCFG register is 0, or General-Purpose Logic Output 1
(Push-Pull) when GPO bit in the GLOBLCFG register is 1. Connect a resistor
in series when configured as an LED output to set the LED current. Leave
unconnected, if not used. See the LED Matrix section for connection/details.
VA
Digital
Output



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