REVISION C 11/03/15

9

1-TO-21, DIFFERENTIAL HCSL FANOUT BUFFER

851021 DATA SHEET

Differential Clock Input Interface

The CLK/nCLK accepts HCSL, LVDS, LVPECL and LVHSTL and

other differential signals. Both differential signals must meet the VPP

and VCMR input requirements. Figures 3A to 3E show interface

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example in Figure 3A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

Figure 3A. CLK/nCLK Input Driven by an IDT



Open Emitter LVHSTL Driver

Figure 3C. CLK/nCLK Input Driven by a



3.3V LVPECL Driver

Figure 3E. CLK/nCLK Input Driven by a



3.3V HCSL Driver

Figure 3B. CLK/nCLK Input Driven by a



3.3V LVPECL Driver

Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver



R1

50

Ω

R2

50

Ω

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

R3

125

R4

125

R1

84

R2

84

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

3.3V

LVPECL

Differential

Input

HCSL

*R3

*R4

CLK

nCLK

3.3V

3.3V

Differential

Input

3.3V

R1

100

LVDS

CLK

nCLK

3.3V

Differential

Input

Zo = 50

Ω

Zo = 50

Ω