873996 datasheet(11/22 Pages) RENESAS

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REVISION A 11/10/15

873996 DATA SHEET

DIFFERENTIAL-TO-3.3V LVPECL

ZERO DELAY/MULTIPLIER/DIVIDER

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V

= 3.3V, V_REF should be 1.25V and R2/

R1 = 0.609.

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. The 873996

provides separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

, V

CCA

and V

CCOx

should be individually connected to the power supply plane

through vias, and 0.01µF bypass capacitors should be used

for each pin. Figure 1 illustrates this for a generic V

pin and

also shows that V

CCA

requires that an additional 10

Ω resistor

along with a 10µF bypass capacitor be connected to the V

CCA

pin.

FIGURE 1. POWER SUPPLY FILTERING

CCA

μF

.01

μF

3.3V

.01

μF

POWER SUPPLY FILTERING TECHNIQUES

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