873996 datasheet(13/22 Pages) RENESAS

13 / 22 page

REVISION A 11/10/15

873996 DATA SHEET

DIFFERENTIAL-TO-3.3V LVPECL

ZERO DELAY/MULTIPLIER/DIVIDER

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are recom-

mended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that generate

ECL/LVPECL compatible outputs. Therefore, terminating resistors

(DC current path to ground) or current sources must be used for

functionality. These outputs are designed to drive 50

Ω transmission

lines. Matched impedance techniques should be used to maximize

FIGURE 4B. LVPECL OUTPUT TERMINATION

FIGURE 4A. LVPECL OUTPUT TERMINATION

operating frequency and minimize signal distortion. Figures 4A

and 4B show two different layouts which are recommended only

as guidelines. Other suitable clock layouts may exist and it would

be recommended that the board designers simulate to guarantee

compatibility across all printed circuit and clock component process

variations.

TERMINATION FOR LVPECL OUTPUTS

INPUTS:

CLK/nCLK INPUTS

For applications not requiring the use of the differential input, both

CLK and nCLK can be left ﬂoating. Though not required, but for

additional protection, a 1k

Ω resistor can be tied from CLK to ground.

LVCMOS CONTROL PINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVPECL OUTPUTS

All unused LVPECL outputs can be left ﬂoating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left ﬂoating or terminated.

873996 Datasheet(PDF) 13 Page - Renesas Technology Corp