DIFFERENTIAL-TO-3.3V LVPECL

ZERO DELAY/MULTIPLIER/DIVIDER

873996 DATA SHEET

2

REVISION A 11/10/15

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1

PLL_SEL

Input

Pullup

Selects between the PLL and reference clock as the input to the di-

viders. When LOW, selects reference clock.When HIGH, selects PLL.

LVCMOS / LVTTL interface levels.

2

nMR

Input

Pullup

Active LOW Master Reset. When logic LOW, the internal dividers are

reset causing the true outputs Qx to go low and the inverted outputs

nQx to go high. When logic HIGH, the internal dividers and the out-

puts are enabled. LVCMOS / LVTTL interface levels.

3

nINIT

Input

Pullup

When HIGH-to-LOW, resets the input bad flags and aligns CLK_INDI-

CATOR to SEL_CLK. LVCMOS / LVTTL interface levels.

4, 17

V

EE

Power

Negative supply pins.

5

CLK0

Input

Pulldown Non-inverting differential clock input.

6

nCLK0

Input

Pullup/

Pulldown

Inverting differential clock input. V

CC

/2 default when left floating.

7

CLK1

Input

Pulldown Non-inverting differential clock input.

8

nCLK1

Input

Pullup/

Pulldown

Inverting differential clock input. V

CC

/2 default when left floating.

9

EXT_FB

Input

Pulldown Differential external feedback.

10

nEXT_FB

Input

Pullup/

Pulldown

Differential external feedback. V

CC

/2 default when left floating.

11

SEL_CLK

Input

Pulldown

Selects the primary reference clock. When LOW, selects CLK0 as the

primary clock source. When HIGH, selects CLK1 as the primary clock

source. LVCMOS / LVTTL interface levels.

12

BW

Input

Pullup/

Pulldown

Bandwidth control pin. LVCMOS / LVTTL interface levels.

Float (default) = Medium Bandwidth (~800kHz),

1 = High Bandwidth (~2000kHz),

0 = Low Bandwidth (~400kHz).

13, 47

V

CC

Power

Core supply pins.

14, 15, 16

NB0, NB1, NB2

Input

Pullup

Bank B output divider control pins

LVCMOS / LVTTL interface levels.

18, 19, 20

NA0, NA1, NA2

Input

Pullup

Bank A output divider control pins

LVCMOS / LVTTL interface levels.

21, 28

V

CCO_B

Power

Output supply voltage for B Bank outputs.

22, 23

nQB2, QB2

Output

Differential output pair. LVPECL interface levels.

24, 25

nQB1, QB1

Output

Differential output pair. LVPECL interface levels.

26, 27

nQB0, QB0

Output

Differential output pair. LVPECL interface levels.

29, 36

V

CCO_A

Power

Output supply voltage for A Bank outputs.

30, 31

nQA2, QA2

Output

Differential output pair. LVPECL interface levels.

32, 33

nQA1, QA1

Output

Differential output pair. LVPECL interface levels.

34, 35

nQA0, QA0

Output

Differential output pair. LVPECL interface levels.

37

V

CCO_FB

Power

Output supply voltage for FB output.

38, 39

QFB, nQFB

Output

Feedback outputs. LVPECL interface levels.

40

V

CCA

Power

Analog supply pin.

41, 42, 43

NFB0, NFB1, NFB2

Input

Pullup

Feedback divider control pins. LVCMOS / LVTTL interface levels.

44

CLK_INDICATOR

Output

Clock indicator pin. When LOW, CLK0, nCLK0 is selected. When

HIGH, CLK1, nCLK1 is selected. LVCMOS / LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

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