6

Device functional description

The STEF512SRI embeds a 5 V and a 12 V electronic fuses (eFuses). Each eFuse can limit the voltage or the

current during fault events, such as input overvoltage or output overload, respectively. For this purpose, it contains

2 hysteretic control loops, one for limiting the output voltage and the other for limiting the input current.

The current limiting loop is also used during the startup phase of the eFuse to limit the in-rush current into the

output capacitor.

During normal operation the eFuse behaves as a low-resistance Power FET, therefore the output voltage follows

the input one. In case of an overvoltage or overcurrent event, the eFuse limits the VGS of the internal FET, to

clamp the output voltage or current respectively. During such events the die temperature increases due to the

power dissipation and so, if the fault persists and the overtemperature threshold is overcome, the device goes into

thermal shutdown, the internal FET is turned off and the load disconnected from the power supply.

Each eFuse provides factory-trimmed undervoltage lockout and output voltage rise time.

The power stage of the 5 V channel consists of 2 MOSFETS connected in a back-to-back configuration. This

configuration is used to perform the reverse current blocking feature in case of input power loss.

The current flowing into each eFuse is continuously sensed through a dedicated copy-MOS and feed to the

current monitor circuit. The current monitor signal generated by this circuit is provided on a single IMON pin, which

outputs either the 5 V or the 12 V channel depending on the logic status of the IMON selection pin (IMON_SEL).

6.1

Undervoltage lockout

The undervoltage lockout circuit prevents each eFuse from turning on if the supply voltage is below the UVLO

rising threshold. During operation, if the input voltage of one channel falls below (VUVLO_x - VHyst_x), the outputs

of both channels are turned off simultaneously.

6.2

Startup sequence and voltage clamp

The typical startup sequence of the eFuse, when the SAS-ignore function is not used (SATAIG pin left floating), is

described below and shown in Figure 4 and Figure 5:

•

The power supply is connected to the VIN_x pins and both 5 V and 12 V input voltages are higher than the

relevant undervoltage lockout threshold.

•

The SATAIG pin is internally pulled up and latched once the internal regulator is active.

•

The SAS-disable pin (EN) is connected to GND or left floating by the user to enable the device.

•

After an initial delay of 500 µs the eFuse starts ramping up the 5 and 12 V output voltages with a fixed

slew-rate, to ensure a 13 ms (typ.) soft-start time and minimize the in-rush current.

•

During the startup phase, the foldback current limit is disabled and the current limit is set to the IHOLD_x

value.

•

If the input voltage continues rising, above the overvoltage threshold (VClamp_x), because of a failure in

the power supply, the eFuse limits the output voltage to VClamp_x. The eFuse keeps operating in this state

until the overtemperature threshold is reached and then it shuts down. The power MOSFET remains in an

off-state until the die temperature drops by the overtemperature hysteresis, then the device automatically

attempts to restart.

Figure 4. Typical startup sequence (EN toggled after VIN rise)

500µs

_

_

_

_

EN

SATAI

G

This transition of SATAIG pin is ignored because its

status is already latched (HIGH state)

VIN Rails

VOUT Rails

5V UVLO

12V UVLO

VIN_5

VIN_12

VOUT_12

VOUT_5

Soft-start

STEF512SRI

Device functional description

DS14138 - Rev 1

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