Figure 7. Startup sequence (SATAIG connected to GND at power-up)

100µs

SAS disable

signal is ignored

This transition of SATAIG pin

generates latched state

This transition of SATAIG pin is ignored

because its status is already latched (HIGH state)

_

_

_

_

EN

SATAI

G

VIN Rails

VOUT Rails

5V UVLO

12V UVLO

VIN_5

VIN_12

VOUT_12

VOUT_5

Soft-start

6.4

Current limit function after startup

Each eFuse provides 2 kinds of current limit protection mechanisms (see Figure 8):

•

Operative current limit (IHOLD_x) for both channels, active once the output voltage reaches the input

voltage.

•

Short-circuit current limit (ISHORT_x) is applied when the output voltage falls below the short-circuit detection

thresholds (2.5 V for the 5 V eFuse and 7.5 V for the 12 V eFuse).

Figure 8. Current limit function graphs

VOUT_5

5V

2.5V

ISHORT_5

IHOLD_5

IIN_5

VOUT_12

12V

7.5V

IIN_12

ISHORT_12

IHOLD_12

6.5

eFuse current monitor

Each channel is equipped with a current monitoring feature that allows the host processor to read the current

flowing through the fuse. To use only one ADC, the IMON_5/12 pin is able to manage both outputs current

information, thanks to a current monitoring selection pin ( IMON_SEL ).

If IMON_SEL is connected to GND, pin 7 outputs the IMON_5 signal. If it is left floating, pin 7 outputs the IMON_12

signal.

It is recommended to drive the IMON_SEL pin via an open-drain circuit.

The IMON_x signal is a current proportional to the relevant channel load current, by factor AI_x = IMON_x / IOUT_x.

This current is imposed on an external RMON_x, converting the sensing current into voltage for further processing

by the host system (see Figure 9).

STEF512SRI

Current limit function after startup

DS14138 - Rev 1

page 10/28