TSB81BA3DPFP datasheet(20/59 Pages) TI

20 / 59 page

TSB81BA3D, TSB81BA3DI

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected

by writing 1 to the Page_Select field in base register 7. Table 5 shows the configuration of the vendor

identification page, and Table 6 shows the corresponding field descriptions.

Table 5. Page 1 (Vendor ID) Register Configuration

BIT POSITION

Address

1000

Compliance

1001

Reserved

1010

Vendor_ID[0]

1011

Vendor_ID[1]

1100

Vendor_ID[2]

1101

Product_ID[0]

1110

Product_ID[1]

1111

Product_ID[2]

Table 6. Page 1 (Vendor ID) Register Field Descriptions

FIELD

SIZE

TYPE

DESCRIPTION

Compliance

Compliance level. For the TSB81BA3D this field is 02h, indicating compliance with the P1394b specification.

Vendor_ID

Manufacturer’s organizationally unique identifier (OUI). For the TSB81BA3D this field is 08_00_28h (Texas

Instruments) (the MSB is at register address 1010b).

Product_ID

Product identifier. For the TSB81BA3D this field is 83_13_06h (the MSB is at register address 1101b).

The vendor-dependent page provides access to the special control features of the TSB81BA3D, as well as

configuration and status information used in manufacturing test and debug. This page is selected by writing 7

to the Page_Select field in base register 7. Table 7 shows the configuration of the vendor-dependent page, and

Table 8 shows the corresponding field descriptions.

Table 7. Page 7 (Vendor-Dependent) Register Configuration

BIT POSITION

Address

1000

Reserved

1001

Reserved for test

1010

Reserved for test

1011

Reserved for test

1100

Reserved for test

1101

Reserved for test

1110

SWR

Reserved for test

1111

Reserved for test

Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions

FIELD

SIZE

TYPE

DESCRIPTION

SWR

Rd/Wr

Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (same effect as momentarily

asserting the RESETz terminal low). This bit is always read as a 0.

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