6.42

70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

2

Jun.04.21

Description

TheIDT70V261isahigh-speed16Kx16Dual-PortStaticRAM.The

IDT70V261isdesignedtobeusedasastand-alone256K-bitDual-Port

RAMorasacombinationMASTER/SLAVEDual-PortRAMfor32-bit-or-

more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM

approach in 32-bit or wider memory system applications results in full-

speed,error-freeoperationwithouttheneedforadditionaldiscretelogic.

This device provides two independent ports with separate control,

address,andI/Opinsthatpermitindependent,asynchronousaccessfor

reads or writes to any location in memory. An automatic power down

featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter

a very low standby power mode.

Fabricated using CMOS high-performance technology, these de-

vices typically operate on only 300mW of power.

The IDT70V261 is packaged in a 100-pin Thin Quad Flatpack.

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

Pin Names

Pin Configurations(1,2,3)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

3040 drw 02

I/O9L

I/O8L

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

GND

I/O1L

I/O0L

OEL

VCC

R/

WL

SEML

CEL

UBL

LBL

A12L

A11L

A10L

I/O7R

I/O8R

I/O9R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

GND

I/O15R

OER

R/

WR

SEMR

CER

UBR

LBR

GND

A12R

A11R

A10R

A9R

A8R

A7R

A6R

A13L

A13R

70V261

PNG100(4)

A9L

A8L

A7L

Left Port

Right Port

Names

CEL

CER

Chip Enable

R/WL

R/WR

Read/Write Enable

OEL

OER

Output Enable

A0L - A13L

A0R - A13R

Address

I/O0L - I/O15L

I/O0R - I/O15R

Data Input/Output

SEML

SEMR

Semaphore Enable

INTL

INTR

Interrupt Flag

UBL

UBR

Upper Byte Select

LBL

LBR

Lower Byte Select

BUSYL

BUSYR

Busy Flag

M/S

Master or Slave Select

VCC

Power

GND

Ground

3040 tbl 01