15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/

LVTTL ZERO DELAY CLOCK BUFFER

86004 DATA SHEET

2

REVISION B 7/10/15

Input

Output

F_SEL

0

Ref ÷8

1

Ref ÷16

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1

Input

Input/Output

Frequency Range (MHz)

F_SEL

Minimum

Maximum

0

31.25

62.5

1

15.625

31.25

TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

C

PD

Power Dissipation Capacitance

(per output)

V

DD

, V

DDA

, V

DDO

= 3.465V

23

pF

V

DD

, V

DDA

, V

DDO

= 2.625V

17

pF

R

OUT

Output Impedance

3.3V ± 5%

5

7

12

Ω

Number

Name

Type

Description

1, 3,

13, 15

Q1, Q0,

Q3, Q2

Output

Clock outputs. 7

Ω

typical output impedance. LVCMOS/LVTTL interface levels.

2, 7, 14

GND

Power

Power supply ground.

4

F_SEL

Input

Pulldown

Frequency range select input. See Table 3A and 3B.

LVCMOS/LVTTL interface levels.

5V

DD

Power

Core supply pin.

6

CLK

Input

Pulldown LVCMOS/LVTTL clock input.

8V

DDA

Power

Analog supply pin.

9

PLL_SEL

Input

Pullup

Selects between the PLL and reference clock as input to the dividers.

When LOW, selects the reference clock (PLL Bypass). When HIGH,

selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.

10

FB_IN

Input

Pulldown

Feedback input to phase detector for regenerating clocks with “zero delay”.

Connect to one of the outputs. LVCMOS/LVTTL interface levels.

11

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the outputs to go low. When logic LOW, the internal dividers and the

outputs are enabled. LVCMOS/LVTTL interface levels.

12, 16

V

DDO

Power

Output supply pins.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.