AT43USB351M datasheet(18/101 Pages) ATMEL

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AT43USB351M

3302E–USB–7/04

Functional Description

On-chip Power

Supply

The AT43USB351M contains three on-chip power supplies that generate 3.3V with a capacity

of 30 mA each from the 5V power input. The on-chip power supplies are intended to supply

the AT43USB351M internal circuit and the 1.5K pull-up resistor only and should not be used

for other purposes. External 2.2 µF filter capacitors are required at the power supply outputs,

CEXT1 and CEXT2 and 0.33 µFal CEXTA. The internal power supplies can be disabled as

described in the next paragraph.

The user should be careful when the GPIO pins are required to supply high-load currents. If

the application requires that the GPIO supply currents beyond the capability of the on-chip

power supply, the AT43USB351M should be supplied by an external 3.3V power supply. In

this case, the 5V V

CC power supply pin should be left unconnected and the external 3.3V

power supplied to the chip through the CEXT1, CEXT2 and CEXTA pins.

I/O Pin

Characteristics

The I/O pins of the AT43USB351M should not be directly connected to voltages less than V

or more than the voltage at the voltage regulator pins. If it is necessary to violate this rule,

insert a series resistor between the I/O pin and the source of the external signal source that

limits the current into the I/O pin to less than 2 mA. Under no circumstance should the external

voltage exceed 5.5V. To do so will put the chip under excessive stress.

Oscillator and PLL

All clock signals required to operate the AT43USB351M are derived from an on-chip oscillator

and a 6 MHz crystal or resonator (low-speed only). In full-speed mode, an on-chip PLL gener-

ates the high frequency for the clock/data separator of the Serial Interface Engine. In the

suspended state, the oscillator circuitry is turned off. In low-speed mode, the PLL is disabled.

The oscillator of the AT43USB351M is a special, low-drive type, designed to work with most

crystals without any external components. The crystal must be of the parallel resonance type

requiring a load capacitance of about 10 pF. If the crystal requires a higher value capacitance,

external capacitors can be added to the two terminals of the crystal and ground to meet the

required value. To assure quick start-up, a crystal with a high Q, or low ESR, should be used.

If the AT43USB351M is to operate in full-speed USB mode, the crystal should have an accu-

racy and stability of better than 100 PPM. The use of a ceramic resonator in place of the

crystal is not recommended for full-speed USB, because a resonator would not have the nec-

essary frequency accuracy and stability.

The clock can also be externally sourced. In this case, connect the clock source to the XTAL1

pin, while leaving XTAL2 pin floating. The switching level at the OSC1 pin can be as low as

0.47V and a CMOS device is required to drive this pin to maintain good noise margins at the

low switching level.

For proper operation of the PLL, an external RC filter consisting of a series RC network of

100

Ω and 0.1 µF in parallel with a 0.01 µF capacitor must be connected from the LFT pin to

SS. Use only high-quality ceramic capacitors.

AT43USB351M Datasheet(PDF) 18 Page - ATMEL Corporation

AT43USB351M Datasheet(HTML) 18 Page - ATMEL Corporation

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