AD7142 datasheet(5/68 Pages) AD

Part #	AD7142

Description	Programmable Capacitance-to-Digital Converter with Environmental Compensation

PDF	68 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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AD7142

Rev. 0 | Page 5 of 68

SPI TIMING SPECIFICATIONS (AD7142)

TA = −40°C to +85°C; VDRIVE = 1.65 V to 3.6 V; AVCC, DVCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure

compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.

Table 4. SPI Timing Specifications

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK

MHz max

ns min

CS falling edge to first SCLK falling edge

ns min

SCLK high pulse width

ns min

SCLK low pulse width

ns min

SDI setup time

ns min

SDI hold time

ns max

SDO access time after SCLK falling edge

ns max

CS rising edge to SDO high impedance

ns min

SCLK rising edge to CS high

SCLK

SDI

SDO

116

MSB

LSB

MSB

LSB

Figure 2. SPI Detailed Timing Diagram

AD7142 Datasheet(PDF) 5 Page - Analog Devices