L6572

Functional description

Doc ID 023882 Rev 1

13/22

5.9

Undervoltage lockout

After the turn-on of the ballast, the UVLO is activated until the supply voltage exceeds the

specified turn-on threshold voltage VSUVP.

While loading the blocking capacitor after power on, the low-side transistor has to be turned

on to charge the bootstrap capacitor before the high-side transistor is switched on the first

time.

When the supply voltage falls below the VSUVN threshold the device waits for the condition

"activated LVG and deactivated HVG". The UVLO is activated with a delay time of 1.3

μs

after this condition comes true.

Moreover, a logic UVLO is activated in order to restart the device with the preheating phase

when no resonant current is sensed in a period of tdisc.

During the logic UVLO, all logic blocks of the device are reset, but the current references

and internal regulators are still on.

5.10

Voltage reference

The voltage reference delivers a reference signal with a very small tolerance (band gap).

5.11

Ignition recognition

This unit is activated at the beginning of the ignition phase (see Figure 6). It provides a

synchronization pulse to the clock generator every time either the current control units are

triggered by the signal processing unit or ZVS control turns on the relevant transistor. Being

the half of the clock frequency programmed to be lower than resonance frequency, the clock

period during the ignition phase is forced to be shorter than the programmed one.

Once the lamp ignites the integral of the operating current, it takes longer time to reach the

rated value and the clock period reaches the programmed value.

In this case, the ignition phase is terminated, the ignition recognition unit is deactivated and

the rated resonant current is set on the powerboost level.

On the contrary, the end of ignition is not detected and both the half-bridge and the clock

remain locked to resonance frequency by ZVS control unit.

5.12

Clock generator

This high frequency oscillator provides with time bases for the IC during the various

operating phases.

During the preheating phase it delivers a fixed time base for the counter. At the beginning of

the ignition phase when the ignition recognition unit is active, the oscillator is synchronized

with the output stage. Therefore the timing element of the oscillator is reset with the

frequency of the output stage. If one half cycle, of period time of the output stage given by

the current regulator exceeds the fixed period time of the clock generator, a trigger signal is

formed and given to the output stage and the counter. This leads to a defined termination of

the ignition phase. After setting the rated resonant current to the powerboost level, the clock

generator continues in a self-oscillating way until it is stopped by the counter at the end of

the powerboost phase.