MPC9350 REVISION 7 March 11, 2016

4

©2012 Integrated Device Technology, Inc.

MPC9350 Data Sheet

Low Voltage PLL Clock Driver

Table 4. DC Characteristics (VCC = 3.3 V  5%, TA = -40° to 85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VIH

Input high voltage

2.0

VCC + 0.3

V

LVCMOS

VIL

Input low voltage

–0.3

0.8

V

LVCMOS

VOH

Output High Voltage

2.4

V

IOH = –24 mA

(1)

1. The MPC9350 is capable of driving 50

 transmission lines on the incident edge. Each output drives one 50  parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines.

VOL

Output Low Voltage

0.55

0.30

V

V

IOL = 24 mA

IOL = 12 mA

IIN

Input Current

200

A

VIN = 0 V or VIN = VCC

ZOUT

Output impedance

14 – 17



CIN

Input capacitance

4.0

pF

CPD

Power Dissipation Capacitance

10

pF

Per Output

ICCA

Maximum PLL Supply Current

10

mA

VCCA Pin

ICC

Maximum Quiescent Supply Current

1.0

mA

All VCC Pins

VTT

Output termination voltage

VCC2

V

Table 5. Characteristics (VCC = 3.3 V  5% or VCC = 2.5 V  5%, TA = -40° to 85°C)

(1)

1. AC characteristics apply for parallel output termination of 50

 to V

TT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

 16 feedback

 32 feedback

Static Test Mode

12.5

6.25

0

25

12.5

300

MHz

MHz

MHz

FBSEL = 1

FBSEL = 0

PLL_EN = 0

fXTAL

Crystal Oscillator Frequency

10

25

MHz

XTAL inputs

fVCO

VCO Frequency

200

400

MHz

PLL_EN = 1

fMAX

Maximum Output Frequency

 2 output

 4 output

 8 output

100

50

25

200

100

50

MHz

MHz

MHz

frefDC

Reference Input Duty Cycle

25

75

%

tr, tf

TLCK Input Rise/Fall Time

VCC = 2.5 V

VCC = 3.3 V

1.0

1.0

ns

ns

0.7 V to 1.7 V

0.8 V to 2.0 V

tsk(o)

Output-to-output Skew

45

150

ps

tPW

Output Duty Cycle

45

50

55

ps

T=Clock period

tr, tf

Output Rise/Fall Time

0.1

0.5

1.0

ns

see Figure 10

tPLZ, HZ

Output Disable Time

10

ns

tPZL, LZ

Output Enable Time

10

ns

BW

PLL closed loop bandwidth

 16 feedback (V

CC = 3.3 V)

 16 feedback (V

CC = 2.5 V)

 32 feedback (V

CC = 3.3 V)

 32 feedback (V

CC = 2.5 V)

2.0 – 8.0

1.0 – 4.0

1.5 – 3.5

0.7 – 2.0

MHz

MHz

MHz

MHz

tJIT(CC)

Cycle-to-cycle jitter

single frequency

multiple frequencies

30

100

200

300

ps

ps

tJIT(PER)

Period Jitter

 16 feedback

 32 feedback

30

80

150

200

ps

ps

tLOCK

Maximum PLL Lock Time

1

ms

tJIT()

I/O Phase Jitter (RMS)

5 – 20

ps

RMS value