MPC9350 REVISION 7 March 11, 2016

8

©2012 Integrated Device Technology, Inc.

MPC9350 Data Sheet

Low Voltage PLL Clock Driver

output-to-output skew of the MPC9350. The output waveform

in Figure 5 shows a step in the waveform. This step is caused

by the impedance mismatch seen looking into the driver. The

parallel combination of the 36

 series resistor plus the

output impedance does not match the parallel combination of

the line impedances. The voltage wave launched down the

two lines will equal:

VL =VS (Z0  (RS+R0 +Z0))

Z0 =50 || 50 

RS =36 || 36 

R0 =17

VL = 3.0 (25  (18+17+25))

= 1.25 V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.5 V. It will then increment

toward the quiescent 3.0 V in steps separated by one round

trip delay (in this case 4.0 ns).

Figure 5. Single versus Dual Waveforms

Since this step is well above the threshold region, it will not

cause any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines, the

situation in Figure 6 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance, the line

impedance is perfectly matched.

Figure 6. Optimized Dual Line Termination

Figure 7. TCLK MPC9350 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V

Time (ns)

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

OutB

tD = 3.9386

OutA

tD = 3.8956

In

14



MPC9350

Output

Buffer

RS = 22

ZO = 50

RS = 22

ZO = 50

14

+ 22 || 22 = 50 || 50

25

 = 25

Pulse

Generator

Z = 50



RT = 50

ZO = 50

RT = 50

ZO = 50

MPC9350 DUT

VTT

VTT