REVISION 9 3/15/16

5

3.3V, 2.5V, 1:9 LVCMOS CLOCK FANOUT BUFFER

MPC9447 DATA SHEET

Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = -40°C to +85°C)

(1)

1. AC characteristics apply for parallel output termination of 50

 to V

TT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

0

350

MHz

fmax

Output Frequency

0

350

MHz

fP,REF

Reference Input Pulse Width

1.4

ns

tr, tf

CCLK0, CCLK1 Input Rise/Fall Time

1.0(2)

2. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

ns

0.7 to 1.7 V

tPLH/HL

Propagation Delay

CCLK0 or CCLK1 to any Q

1.7

4.4

ns

tPLZ, HZ

Output Disable Time

11

ns

tPZL, ZH

Output Enable Time

11

ns

tS

Setup Time

CCLK0 or CCLK1 to CLK_STOP(3)

3. Setup and hold times are referenced to the falling edge of the selected clock signal input.

0.0

ns

tH

Hold Time

CCLK0 or CCLK1 to CLK_STOP(3)

1.0

ns

tsk(O)

Output-to-Output Skew

150

ps

tsk(PP)

Device-to-Device Skew

2.7

ns

tSK(P)

DCQ

Ouput Pulse Skew(4)

Output Duty Cycle

fQ<350 MHz

4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.

45

50

200

55

ps

%

DCREF = 50%

tr, tf

Output Rise/Fall Time

0.1

1.0

ns

0.6 to 1.8 V

tJIT

Buffer Additive Phase Jitter, RMS

0.03

ps

156.25MHz,

Integration Range:

12kHz - 20MHz