MPC9658 REVISION 6 JANUARY 8, 2013

6

©2013 Integrated Device Technology, Inc.

MPC9658 Data Sheet

3.3V 1:10 LVCMOS PLL CLOCK GENERATOR

APPLICATIONS INFORMATION

Programming the MPC9658

The MPC9658 supports output clock frequencies from 50

to 250 MHz. Two different feedback divider configurations

can be used to achieve the desired frequency operation

range. The feedback divider (VCO_SEL) should be used to

situate the VCO in the frequency lock range between 200 and

500 MHz for stable and optimal operation. Two operating

frequency ranges are supported: 50 to 125 MHz and 100 to

250 MHz. Table 7. MPC9658 Configurations (QFB connected

to FB_IN) illustrates the configurations supported by the

MPC9658. PLL zero-delay is supported if BYPASS =1,

PLL_EN = 1, and the input frequency is within the specified

PLL reference frequency range.

Power Supply Filtering

The MPC9658 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise

on the VCCA_PLL power supply impacts the device

characteristics, for instance I/O jitter. The MPC9658 provides

separate power supplies for the output buffers (VCC) and the

phase-locked loop (VCCA_PLL) of the device. The purpose of

this design technique is to isolate the high switching noise

digital outputs from the relatively sensitive internal analog

phase-locked loop. In a digital system environment where it

is more difficult to minimize noise on the power supplies a

second level of isolation may be required. The simple but

effective form of isolation is a power supply filter on the

VCC_PLL pin for the MPC9658. Figure 3 illustrates a typical

power supply filter scheme. The MPC9658 frequency and

phase stability is most susceptible to noise with spectral

content in the 100 kHz to 20 MHz range. Therefore the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

drop across the series filter resistor RF. From the data sheet

the ICC_PLL current (the current sourced through the

VCC_PLL pin) is typically 12 mA (20 mA maximum), assuming

that a minimum of 2.835 V must be maintained on the

VCC_PLL pin.

Figure 3. VCC_PLL Power Supply Filter

The minimum values for RF and the filter capacitor CF are

defined by the required filter characteristics: the RC filter

should provide an attenuation greater than 40 dB for noise

whose spectral content is above 100 kHz. In the example RC

filter shown in Figure 3, the filter cut-off frequency is around

3 – 5 kHz and the noise attenuation at 100 kHz is better than

42 dB.

As the noise frequency crosses the series resonant point

of an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above

the bandwidth of the PLL. Although the MPC9658 has

several design features to minimize the susceptibility to

power supply noise (isolated power and grounds and fully

differential PLL) there still may be applications in which

overall performance is being degraded due to system power

supply noise. The power supply filter schemes discussed in

this section should be adequate to eliminate power supply

noise related problems in most designs.

Using the MPC9658 in Zero-Delay Applications

Nested clock trees are typical applications for the

MPC9658. Designs using the MPC9658 as LVCMOS PLL

fanout buffer with zero insertion delay will show significantly

lower clock skew than clock distributions developed from

CMOS fanout buffers. The external feedback option of the

MPC9658 clock driver allows for its use as a zero delay

buffer. The PLL aligns the feedback clock output edge with

the clock input reference edge resulting a near zero delay

through the device (the propagation delay through the device

is virtually eliminated). The maximum insertion delay of the

device in zero-delay applications is measured between the

reference clock input and any output. This effective delay

consists of the static phase offset, I/O jitter (phase or

long-term jitter), feedback path delay and the

output-to-output skew error relative to the feedback output.

Table 7. MPC9658 Configurations (QFB connected to FB_IN)

BYPASS

PLL_EN

VCO_SEL

Operation

Frequency

Ratio

Output range (fQ0–9)

VCO

0

X

X

Test mode: PLL and divider bypass

fQ0–9 = fREF

0 – 250 MHz

n/a

1

0

0

Test mode: PLL bypass

fQ0–9 = fREF  2

0 – 125 MHz

n/a

1

0

1

Test mode: PLL bypass

fQ0–9 = fREF  4

0 – 62.5 MHz

n/a

1

1

0

PLL mode (high frequency range)

fQ0–9 = fREF

100 – 250 MHz

fVCO = fREF  2

1

1

1

PLL mode (low frequency range)

fQ0–9 = fREF

50 – 125 MHz

fVCO = fREF  4

VCC_PLL

VCC

MPC9658

10 nF

RF = 5–15 

CF = 22F

CF

33...100 nF

RF

VCC