MPC9658 REVISION 6 JANUARY 8, 2013

7

©2013 Integrated Device Technology, Inc.

MPC9658 Data Sheet

3.3V 1:10 LVCMOS PLL CLOCK GENERATOR

Calculation of Part-to-Part Skew

The MPC9658 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC9658 are connected together, the maximum overall

timing uncertainty from the common PCLK input to any output

is:

tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()  CF

This maximum timing uncertainty consist of four

components: static phase offset, output skew, feedback

board trace delay, and I/O (phase) jitter:

Figure 4. MPC9658 Max. Device-to-Device Skew

Due to the statistical nature of I/O jitter a RMS value (1

)

is specified. I/O jitter numbers for other confidence factors

(CF) can be derived from Table 8.

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation a

I/O jitter confidence factor of 99.7% (

 3) is assumed,

resulting in a worst case timing uncertainty from input to any

output of –214 ps to 224 ps relative to PCKL (fREF = 100 MHz,

FB = ³4, tjit() = 8 ps RMS at fVCO = 400 MHz):

tSK(PP) = [–70ps...80ps] + [–120ps...120ps] +

[(8ps

 –3)...(8ps  3)] + tPD, LINE(FB)

tSK(PP) = [–214ps...224ps] + tPD, LINE(FB)

Due to the frequency dependence of the I/O jitter, Figure 5

can be used for a more precise timing performance analysis.

Figure 5. Max. I/O Jitter versus Frequency

Driving Transmission Lines

The MPC9658 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user, the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20

 the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines, the reader is referred to Freescale Semiconductor

Application Note AN1091. In most high performance clock

networks, point-to-point distribution of signals is the method

of choice. In a point-to-point scheme, either series terminated

or parallel terminated transmission lines can be used. The

parallel technique terminates the signal at the end of the line

with a 50

 resistance to VCC  2.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9658 clock driver. However, for the series

terminated case there is no DC current draw, thus the

outputs can drive multiple series terminated lines. Figure 6

illustrates an output driving a single series terminated line

versus two series terminated lines in parallel. When taken to

its extreme, the fanout of the MPC9658 clock driver is

effectively doubled due to its capability to drive multiple lines.

Table 8. Confidence Factor CF

CF

Probability of clock edge within the distribution

 1

0.68268948

 2

0.95449988

 3

0.99730007

 4

0.99993663

 5

0.99999943

 6

0.99999999

tPD,LINE(FB)

tJIT()

+tSK(O)

—t(ý)

+t()

tJIT()

+tSK(O)

tSK(PP)

Max. skew

TCLKCommon

QFBDevice 1

Any QDevice 1

QFBDevice2

Any QDevice 2

FCO Frequency [MHz]

200

250

300

350

400

450

500

FB = ³ 4

FB = ³ 2

0

15

10

5

20

I/O Phase Jitter versus Frequency

Parameter: PLL Feedback Divider FB