| Electronic Components Datasheet Search |
|
MPC9658 Datasheet(PDF) 8 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
MPC9658 Datasheet(HTML) 8 Page - Renesas Technology Corp |
|
8 / 13 page ![]() MPC9658 REVISION 6 JANUARY 8, 2013 8 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9658 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9658. The output waveform in Figure 7 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL =VS (Z0 (RS+R0 +Z0)) Z0 =50 || 50 RS =36 || 36 R0 =14 VL = 3.0 (25 (18+14+25) =1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering. However, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 8 should be used. In this case, the series terminating resistors are reduced such that, when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. Figure 8. Optimized Dual Line Termination Figure 9. PCLK MPC9658 AC Test Reference 14 In MPC958 Output Buffer RS = 36 ZO = 50 OutA 14 In MPC958 Output Buffe RS = 36 ZO = 50 OutB0 RS = 36 ZO = 50 OutB1 Time (ns) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 OutB tD = 3.9386 OutA tD = 3.8956 In 14 MPC958 Output Buffe RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Pulse Generator Z = 50 RT = 50 ZO = 50 RT = 50 ZO = 50 MPC9658 DUT VTT VTT |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |