MPC9773 datasheet(11/22 Pages) RENESAS

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MPC9773 REVISION 6 MARCH 16, 2016

MPC9773 Data Sheet

3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR

SYNC Output Description

The MPC9773 has a system synchronization pulse output

QSYNC. In configurations for which the output frequency

relationships are not integer multiples of each other, QSYNC

provides a signal for system synchronization purposes. The

MPC9773 monitors the relationship between the A bank and

the B bank of outputs. The QSYNC output is asserted (logic

low) one period in duration and one period prior to the

coincident rising edges of the QA and QC outputs. The

duration and the placement of the pulse is dependent on QA

and QC output frequencies: the QSYNC pulse width is equal

to the period of the higher of the QA and QC output

frequencies. Figure 6 shows various waveforms for the

QSYNC output. The QSYNC output is defined for all possible

combinations of the bank A and bank C outputs.

Figure 6. QSYNC Timing Diagram

fVCO

1:1 Mode

QSYNC

2:1 Mode

QC(

2)

QA(

6)

QSYNC

3:1 Mode

QSYNC

QA(

4)

QC(

6)

QSYNC

3:2 Mode

QC(

2)

QA(

8)

QSYNC

4:1 Mode

QA(

6)

QC(

8)

QSYNC

4:3 Mode

QA(

12)

QC(

2)

QSYNC

6:1 Mode

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