X40410V8-C datasheet(13/24 Pages) RENESAS

13 / 24 page

X40410, X40411, X40414, X40415

FN8116 Rev 0.00

Page 13 of 24

March 28, 2005

Figure 15. Random Address Read Sequence

– One bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte defines the opera-

tion to be performed. When the R/W bit is a one, then

a read operation is selected. A zero selects a write

operation.

Word Address

The word address is either supplied by the master or

obtained from an internal counter. The internal counter is

undefined on a power-up condition.

Operational Notes

The device powers-up in the following state:

– The device is in the low power standby state.

– The WEL bit is set to ‘0’. In this state it is not possible

to write to the device.

– SDA pin is the input mode.

– RESET/RESET Signal is active for tPURST.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– The WEL bit must be set to allow write operations.

– The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile write

cycle.

– A three step sequence is required before writing into

the Control Register to change Watchdog Timer or

Block Lock settings.

Figure 16. Sequential Read Sequence

Slave

Address

Byte

Address

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

10 1

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(n-1)

(n is any integer greater than 1)

Data

(1)

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