X40410, X40411, X40414, X40415

FN8116 Rev 0.00

Page 2 of 24

March 28, 2005

Low VCC detection circuitry protects the user’s system

from low voltage conditions, resetting the system when

VCC falls below the minimum VTRIP1 point. RESET/RE-

SET is active until VCC returns to proper operating level

and stabilizes. A second voltage monitor circuit tracks the

unregulated supply to provide a power fail warning or

monitors different power supply voltage. Three common

low voltage combinations are available, however, Inter-

sil’s unique circuits allows the threshold for either voltage

monitor to be reprogrammed to meet special needs or to

fine-tune the threshold for applications requiring higher

precision.

The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the micro-

controller fails to restart a timer within a selectable time

out interval, the device activates the WDO signal. The

user selects the interval from three preset values. Once

selected, the interval does not change, even after

cycling the power.

The memory portion of the device is a CMOS Serial

EEPROM array with Intersil’s Block Lock protection. The

array is internally organized as x 8. The device features

a 2-wire interface and software protocol allowing opera-

tion on an I2C® bus.

The device utilizes Intersil’s proprietary Direct Write™

cell, providing a minimum endurance of 100,000 cycles

and a minimum data retention of 100 years.

Triple Voltage Monitors

*Voltage monitor requires VCC to operation. Others are independent of VCC.

PIN CONFIGURATION

Device

Expected System Voltages

Vtrip1(V)

Vtrip2(V)

POR (system)

X4040/11

-A

-B

-C

5V; 3V or 3.3V

5V; 3V

3V; 3.3V; 1.8V

2.0–4.75*

4.55–4.65*

4.35–4.45*

2.85–2.95*

1.70–4.75

2.85–2.95

2.55–2.65

1.65–1.75

RESET = X40410

RESET = X40411

X40414/15

-A

-B

-C

3V; 3.3V; 1.5V

3V; 1.5V

3V or 3.3V; 1.1 or 1.2V

2.0–4.75*

2.85–2.95*

2.55–2.65*

2.85–2.95*

0.90–3.50*

1.25–1.35*

1.25–1.35*

0.95–1.05*

RESET = X40414

RESET = X40415

SDA

VCC

3

2

4

1

6

7

5

8

RESET/RESET

VSS

V2MON

3

2

4

1

6

7

5

8

SCL

WDO

V2FAIL

RESET/RESET

SCL

VSS

SDA

V2FAIL

V2MON

WDO

VCC

X40410/14, X40411/15

X40410/14, X40411/15

8-Pin SOIC

8-Pin TSSOP

PIN DESCRIPTION

Pin

Name

Function

SOIC TSSOP

13

V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and

goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.

24

V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes

LOW. This input can monitor an unregulated power supply with an external resistor divider or can

monitor a second power supply with no external components. Connect V2MON to VSS or VCC when

not used.The V2MON comparator is supplied by V2MON (X40410/11) or by VCC Input (X40414/15).

35

RESET/

RESET

RESET Output.

(X40411/15) This is an active LOW, open drain output which goes active whenever

VCC falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and for the tPURST thereafter.

RESET Output.

(X40410/14) This is an active HIGH CMOS output which goes active whenever VCC

falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and for the tPURST thereafter.

46

VSS

Ground

57

SDA

Serial Data.

SDA is a bidirectional pin used to transfer data into and out of the device. It has an open

drain output and may be wire ORed with other open drain or open collector outputs. This pin requires

a pull up resistor and the input buffer is always active (not gated).

Watchdog Input.

A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to

LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transi-

tion within the watchdog time out period results in WDO going active.