X80140, X80141, X80142, X80143, X80144

FN8153 Rev 0.00

Page 17 of 18

January 20, 2005

Serial Read Operations

Read operations are initiated in the same manner as write

operations with the exception that the R/W bit of the Slave

Address Byte is set to one. There are three basic read

operations: Current Address Reads, Random Reads, and

Sequential Reads.

RANDOM READ

Random read operation allows the master to access any

memory location in the array. Prior to issuing the Slave

Address Byte with the R/W bit set to one, the master must first

perform a “dummy” write operation. The master issues the

START condition and the Slave Address Byte, receives an

acknowledge, then issues the Word Address Bytes. After

acknowledging receipts of the Word Address Bytes, the master

immediately issues another START condition and the Slave

Address Byte with the R/W bit set to one. This is followed by an

acknowledge from the device and then by the eight bit word.

The master terminates the read operation by not responding

with an acknowledge and then issuing a STOP condition. See

Figure 16 for the address, acknowledge, and data transfer

sequence.

CURRENT ADDRESS READ

Internally the device contains an address counter that

maintains the address of the last word read incremented by

one. Therefore, if the last read was to address n, the next read

operation would access data from address n+1. On power up,

the address of the address counter is undefined, requiring a

read or write operation for initialization.

Upon receipt of the Slave Address Byte with the R/W bit set to

one, the device issues an acknowledge and then transmits the

eight bits of the Data Byte. The master terminates the read

operation when it does not respond with an acknowledge

during the ninth clock and then issues a STOP condition. See

Figure 17 or the address, acknowledge, and data transfer

sequence.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• The WEL bit is set to ‘0’. In this state it is not possible to write

to the device.

• SDA pin is the input mode.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

• The WEL bit must be set to allow write operations.

• The proper clock count and bit sequence is required prior to

the STOP bit in order to start a nonvolatile write cycle.

• The WP pin, when held HIGH, prevents all writes to the array

and all the Register.

• A programming voltage must be applied to the VP pin prior to

any programming sequence.

ACK

Returned?

Issue Slave Address

Byte (Read or Write)

Byte Load Completed by

Issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

NO

YES

High Voltage Cycle

Complete. Continue

Command Sequence?

Issue STOP

NO

Continue Normal Read

or Write Command

Sequence

PROCEED

YES

FIGURE 18. ACKNOWLEDGE POLLING SEQUENCE