ADM1062 datasheet(27/32 Pages) AD

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Preliminary Technical Data

ADM1062

Rev. PrJ | Page 27 of 32

SERIAL BUS INTERFACE

Control of the ADM1062 is carried out via the serial System

Management Bus (SMBus). The ADM1062 is connected to this

bus as a slave device, under the control of a master device. It

takes approximately 1ms after power up for the ADM1062 to

download from it's EEPROM. Therefore access is restricted to

the ADM1062 until the download is completed.

IDENTIFYING THE ADM1062 ON THE SMBUS

The ADM1060 has a 7-bit serial bus slave address. When the

device is powered up, it will do so with a default serial bus

address. The five MSB's of the address are set to 00101, the two

LSB's are determined by the logical states of pin A1 and A0.

This allows the connection of 4 ADM1062’s to the one SMBus.

The device also has a number of identification registers (read

only) which can be read across the SMBus. Table 8 lists these

registers, their values, and functions.

Table 8.

Name Address

Value

Function

MANID F4h

41h

Manufacturer ID for Analog Devices

REVID F5h

--h

Silicon Revision

MARK1 F6h

--h

S/w brand

MARK2 F7h

--h

S/w brand

GENERAL SMBUS TIMING

Figure 37, Figure 38 and Figure 39 show timing diagrams for

general read and write operations using the SMBus. The SMBus

specification defines specific conditions for different types of

read and write operation, which are discussed later.

The general SMBus protocol operates as follows:

The master initiates data transfer by establishing a START

condition, defined as a high to low transition on the serial

data line SDA whilst the serial clock line SCL remains high.

This indicates that a data stream will follow. All slave

peripherals connected to the serial bus respond to the

START condition, and shift in the next 8 bits, consisting of

a 7-bit slave address (MSB first) plus a R/W bit, which

determines the direction of the data transfer, i.e. whether

data will be written to or read from the slave device (0 =

write, 1 = read).

The peripheral whose address corresponds to the

transmitted address responds by pulling the data line low

during the low period before the ninth clock pulse, known

as the Acknowledge Bit, and holding it low during the high

period of this clock pulse. All other devices on the bus now

remain idle whilst the selected device waits for data to be

read from or written to it. If the R/W bit is a 0 then the

master will write to the slave device. If the R/W bit is a 1

the master will read from the slave device.

Data is sent over the serial bus in sequences of 9 clock

pulses, 8 bits of data followed by an Acknowledge Bit from

the slave device. Data transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, as a low to high transition

when the clock is high may be interpreted as a STOP

signal. If the operation is a write operation, the first data

byte after the slave address is a command byte. This tells

the slave device what to expect next. It may be an

instruction such as telling the slave device to expect a block

write, or it may simply be a register address that tells the

slave where subsequent data is to be written. Since data can

flow in only one direction as defined by the R/W bit, it is

not possible to send a command to a slave device during a

read operation. Before doing a read operation, it may first

be necessary to do a write operation to tell the slave what

sort of read operation to expect and/or the address from

which data is to be read.

When all data bytes have been read or written, stop

conditions are established. In WRITE mode, the master will

pull the data line high during the 10th clock pulse to assert

a STOP condition. In READ mode, the master device will

release the SDA line during the low period before the 9th

clock pulse, but the slave device will not pull it low. This is

known as No Acknowledge. The master will then take the

data line low during the low period before the 10th clock

pulse, then high during the 10th clock pulse to assert a

STOP condition

SMBUS PROTOCOLS FOR RAM AND EEPROM

The ADM1062 contains volatile registers (RAM) and non-

volatile EEPROM. User RAM occupies address locations from

00h to DFh, whilst EEPROM occupies addresses from F800h to

FBFFh.

Data can be written to and read from both RAM and EEPROM

as single data bytes.

Data can only be written to unprogrammed EEPROM locations.

To write new data to a programmed location it is first necessary

to erase it. EEPROM erasure cannot be done at the byte level,

the EEPROM is arranged as 32 pages of 32 bytes, and an entire

page must be erased.

Page erasure is enabled by setting bit 2 in register UPDCFG

(address 90h) to 1. If this is not set then page erasure cannot

occur, even if the command byte (FEh) is programmed across

the SMBus.

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