LT3756 datasheet(22/31 Pages) AD

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LT8355-1

Rev. A

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APPLICATIONS INFORMATION

and ISN are both near (or at) 0V. The LED current sense

amplifier will continue to command the LED current pro-

grammed by CTRL1,2 and IADJ2 all the way down to 0V

on ISP. However, recall that ISP provides the positive rail

for the driver of the external disconnect PMOS. Therefore,

the use of low side sensing of LED current is not rec-

ommended for applications that use PWM dimming or

for any boost configuration applications requiring output

short circuit protection.

Planning for Thermal Shutdown

The LT8355-1 will automatically shuts down when the

internal temperature is above 170°C (typical). This shut-

down is guaranteed to always be outside of the operating

region of the device. The effects of thermal shutdown

are like that of the load faults: switching stops, soft-start

is reset, and if an external PMOS is used according to

instructions in the PWM Dimming section, the load is

disconnected from the output capacitor. The exposed

pad is ground, and must be soldered to a good, large

ground plane with many vias to aid thermal management.

Since LT8355-1 controls power components and does not

itself conduct any meaningful portion of the load current,

power dissipation in the LT8355-1 may be lower than

a monolithic converter. Power dissipation will increase

with VIN and switching frequency. Die temperature will

increase with power dissipation. Higher ambient tempera-

ture applications will not be able to dissipate as much

power, and high power dissipation in any condition may

overstress die temperature.

PCB Layout Guidelines and Information

Printed Circuit Board (PCB) layout profoundly affects

performance of all power applications. Proper electrical

and thermal connection of the IC and power components

with the outside world will mean the difference between

success or failure of any system. Do not neglect spending

adequate design time on the layout of any application

PCB. The exposed ground pad on the bottom of the pack-

age must be soldered to a ground plane.

The switch current sense resistor RSENSE should connect

to a large, unbroken ground plane. The ground termi-

nal of the switch current sense resistor should be Kelvin

connected to the SENSE1,2 pins of the respective channel

of LT8355-1. Connect the INTVCC bypass capacitor from

the INTVCC pin directly to the exposed pad by the short-

est route possible. Analog and control functions such as

VC1,2; PWM1,2; CTRL1,2; IADJ2; and VREF should have a

separate ground plane, which includes the exposed pad

of the IC. The power and analog ground planes should

meet only in a Kelvin connection to the exposed pad and

at the power input to the PCB.

Be sure to design proper ground planes for power and ana-

log functions within the application PCB. Ground planes

should not be interrupted by other traces, and should

be continuous, very wide sheets of copper. Connect the

exposed pad of the IC to such a ground plane. Use as

many vias as will fit in the exposed pad area to make the

connection. Filled or capped vias may ease soldering for

the exposed pad area. Do not copy any particular layout

for the exposed pad connection, but instead use as many

vias as will fit given the capabilities of the PCB fab house.

In addition to soldering down the exposed pad, it is critical

to provide a good, robust layout for the power path. Use

wide traces for VIN and to connect to the load. Keep the

LED and switch current sense resistors close to the IC

and ensure that the ISP and ISN traces run as close to

one another as possible. It is strongly recommended to

not allow ISP and ISN to take different paths to the LED

current sense resistor, but instead to keep them beside

one another as much as possible. Minimize the total

area of any switching node (SW) traces, keep the output

capacitor and external catch diode as close as possible

to the external NMOS switch and switch current sense

resistor to help this. Finally, use wide traces to connect

to the external PMOS switch, if used. Note, however, that

the gates of both external switches should be connected

by a narrow trace. Except for the external switch gates,

avoid vias where possible in the power path. If vias are

truly unavoidable, use many in parallel. Proper PCB lay-

out is critical for suppressing radiated and conducted

Electromagnetic interference (EMI). Minimizing the area

of the SW node will decrease the amount of capacitance

that the switch sees, and thus reduce the current spike

seen during switching events. Failing to minimize the area

of the so-called hot loop will dramatically degrade EMI

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