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DSP96002/D Datasheet(PDF) 6 Page - NXP Semiconductors |
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DSP96002/D Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 111 page  Signal/Connection Descriptions Signal Groupings 1-2 DSP96002/D, Rev. 2 MOTOROLA Figure 1-1 Functional Group Pin Allocations Address Bus A AA0–AA31 Data Bus A AD0–AD31 Port A Bus Control AS1 AS0 AR/W ABS ABL ATT ATS ATA AAE ADE AHS AHA AHR ABR ABG ABB ABA Interrupt and Mode Control MODA/IRQA MODB/IRQB MODC/IRQC RESET Clock Input CLK Power1 VCCN VCCQ Address Bus B BA0–BA31 Data Bus B BD0 – BD31 Port B Bus Control BS1 BS0 BR/W BBS BBL BTT BTS BTA BAE BDE BHS BHA BHR BR BBG BBB BBA On-Chip Emulation Port (OnCE) DSO DSI/OSO DSCK/OS1 DR DSP96002 32 / 32 / 32 / 32 / AWR BWR Timer/Event Counters TIO0–TIO1 2 Ground2 GNDN GNDQ Note: 1. Number of power input pins is package dependent. See Section 3. 2. Number of ground connections is package dependent. See Section 3. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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