PowerPC 602 RISC Microprocessor Hardware Specifications

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1.1.1 Features

This section describes details of the 602 implementation of the PowerPC architecture. Major features of the

602 are as follows:

•

High-performance, superscalar microprocessor

— As many as two instructions are fetched from the instruction queue per clock

— One instruction can be issued and one retired per clock

— As many as four instructions in execution per clock

— Single-cycle execution for most instructions

•

Four independent execution units and two register files

— BPU performs architecturally-defined static branch prediction

— A 32-bit IU

— Fully IEEE 754-compliant FPU for single-precision operations

— Emulation support for double-precision operations

— An implementation of the non-IEEE floating-point mode

— Thirty-two 32-bit general-purpose registers (GPRs) for integer operands

— Thirty-two 32-bit floating-point registers (FPRs) for single-precision operands

— LSU for data transfer between data cache and GPRs and FPRs

•

Instruction pipelining and split cache organization

— Zero-cycle branch capability (branch folding)

— Programmable static branch prediction on unresolved conditional branches

— BPU that performs CR lookahead operations

— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache

(one of which is a branch instruction)

— A four-entry instruction queue that provides lookahead capability

— Independent pipelines with feed-forwarding that reduces data dependencies in hardware

— 4-Kbyte data cache—two-way set-associative, physically addressed; LRU replacement

algorithm

— 4-Kbyte instruction cache—two-way set-associative, physically addressed; LRU replacement

algorithm

— Cache write-back or write-through operation programmable on a per page or per block basis

•

Memory managament features

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

— A 32-entry, two-way set-associative ITLB

— A 32-entry, two-way set-associative DTLB

— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks

— Software table search operations and updates supported through fast trap mechanism

— 52-bit virtual address; 32-bit physical address

— Optional configuration of the TLBs that offers protection for up to 4-Mbytes of memory per

TLB, but no effective address translation

Freescale Semiconductor, Inc.

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