MMC2001 datasheet(32/259 Pages) NXP

32 / 259 page

MMC2001

INTEGER CPU

MOTOROLA

REFERENCE MANUAL

2-11

2.8.4 Bus Operation

The following sections provide a functional description of the system bus, the signals

that control it, and the bus cycles provided for data transfer operations. They also

describe the error conditions and reset operation.

Table 2-2 M•CORE Bus Signals

Signal Name

Pins

Active

I/O

Description

Address and Transfer Attributes

ADDR[31:0]

Address Bus

High

Driven by the M•CORE to specify the physical address of

the bus transaction.

R/W

Read/Write

1High

Driven by the M•CORE along with the address. Driven

high indicates that a read access is in progress. Driven

low indicates that a write access is in progress.

TSIZ[1:0]

Transfer Size

2High

Driven by the M•CORE along with the address. Specifies

the data transfer size for the transaction.

TC[2:0]

Transfer Code

3High

Driven by the M•CORE along with the address. Indicates

the type of access for the current bus cycle.

Transfer Request/Transfer Busy

TREQ

Transfer Request

1Low

Driven by the M•CORE along with the address and trans-

fer attributes to indicate that a new access has been

requested.

TBUSY

Transfer Busy

1Low

Driven by the M•CORE to indicate that an access is in

progress. This signal is driven for the duration of a cycle

and may be held asserted for multiple transfers.

Data

DATA[31:0]

Data Bus

High

Driven by the M•CORE when it “owns” the bus and it initi-

ated a write transaction to a slave device. Eight (byte), 16

(halfword), or 32 (word) bits of data can be transferred

per access.

Driven by the slave in a read transaction. Eight (byte), 16

(halfword), or 32 (word) bits of data can be transferred

per access.

Transfer Cycle Termination and Status

Transfer Acknowledge

1Low

Driven by the slave device to which the current transac-

tion was addressed. Indicates that the slave has received

the data on the write cycle or returned data on the read

cycle.

TEA

Transfer Error

Acknowledge

1Low

Driven by the slave device to which the current transac-

tion was addressed. Indicates that an error condition has

occurred during the bus cycle.

ABORT

Abort

1Low

Driven by the M•CORE to indicate that the transfer is to

be aborted immediately.

Power Management

LPMD[1:0]

Low-Power Modes

2Low

Driven by the M•CORE to indicate whether the core is

running in normal mode or has just executed a low power

mode instruction.

Debug

DBGACK

Debug Mode

1Low

Driven by the M•CORE to indicate that debug mode has

been entered.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MMC2001 Datasheet(PDF) 32 Page - NXP Semiconductors

MMC2001 Datasheet(HTML) 32 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL