MMC2001 datasheet(80/259 Pages) NXP

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MMC2001

CLOCK MODULE AND LOW-POWER MODES

MOTOROLA

REFERENCE MANUAL

8-7

Power may or may not be available to peripherals (except for the TOD and OSC) and

CPU while in standby mode, depending on the level of VDD. The purpose of this mode

is to enable the SRAM and TOD to remain valid while the state of the other on-chip

components is undefined.

*Dependent on programming

8.2.3 General Low-Power Features

8.2.3.1 Peripheral Shut Down

Each peripheral may be disabled by software in order to cease internal clock genera-

tion and remain in a static state. Each peripheral has its own specific disabling

sequence (refer to each peripheral description for further details).

8.2.3.2 CLKOUT Pin Shut Down

This output pin may be disabled in the low state to lower power consumption via the

CLKOUT enable (CKOE) bit in the reset/timer block.

Table 8-2 CPU Core and Peripherals in Low-Power Modes

Module

Peripheral Clock Status during Mode/Wake-up Capability

Run

Wait

Doze

Stop

Standby

CPU Core

Running

Stopped

UART

Running

Running/Yes

Prog.*/Yes

Stopped/No

ISPI

Running

Running/Yes

Prog.*/Yes

Stopped/No

Interrupt Controller

Running

Stopped/Yes

Stopped/No

EIM

Running

Stopped/No

PWMs

Running

Running/Yes

Prog.*/Yes

Stopped/No

Watchdog Timer

Running

Running/Yes

Prog.*/Yes

Stopped/No

Interval Timer (PIT)

Running

Running/Yes

Prog.*/Yes

Stopped/No

Time-of-Day Timer

(TOD)

Running

Running/Yes

Running/No

GPIO/Keypad

Running

Running/Yes

Stopped/Yes

Stopped/No

OnCE

Running

Running/Yes

Stopped/No

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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