ADT7481 datasheet(17/24 Pages) AD

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ADT7481

Rev. 0 | Page 17 of 24

SERIAL BUS INTERFACE

Control of the ADT7481 is achieved via the serial bus. The

ADT7481 is connected to this bus as a slave device under the

control of a master device.

The ADT7481 has an SMBus timeout feature. When this is

enabled, the SMBus will typically timeout after 25 ms of no

activity. However, this feature is not enabled by default. Set Bit 7

(SCL timeout bit) of the consecutive alert register (Address 0x22)

to enable the SCL timeout. Set Bit 6 (SDA timeout bit) of the

consecutive alert register (Address 0x22) to enable the SDA

timeout.

The ADT7481 supports packet error checking (PEC) and its use

is optional. It is triggered by supplying the extra clock for the

PEC byte. The PEC byte is calculated using CRC-8. The frame

check sequence (FCS) conforms to CRC-8 by the polynomial

()

Consult the SMBus 1.1 specification for more information

(www.smbus.org).

ADDRESSING THE DEVICE

In general, every SMBus device has a 7-bit device address,

except for some devices that have extended, 10-bit addresses.

When the master device sends a device address over the bus,

the slave device with that address responds. The ADT7481 is

available with one device address, 0x4C (1001 100b). An

ADT7481-1 is also available. The only difference between the

ADT7481 and the ADT7481-1 is the SMBus address. The

ADT7481-1 has a fixed SMBus address of 0x4B (1001 011b).

The addresses mentioned in this datasheet are 7-bit addresses.

The R/W bit needs to be added to arrive at an 8-bit address.

Other than the different SMBus addresses, the ADT7481 and

the ADT7481-1 are functionally identical.

The serial bus protocol operates as follows:

The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial data

line (SDATA) while the serial clock line (SCLK) remains high.

This indicates that an address/data stream follows. All slave

peripherals connected to the serial bus respond to the start

condition and shift in the next eight bits, consisting of a 7-bit

address (MSB first) plus a R/W bit, which determines the

direction of the data transfer, that is, whether data will be

written to, or read from, the slave device. The peripheral with

the address corresponding to the transmitted address responds

by pulling the data line low during the low period before the

ninth clock pulse, known as the acknowledge bit. All other

devices on the bus remain idle while the selected device waits

for data to be read from or written to it. If the R/W bit is 0, the

master writes to the slave device. If the R/W bit is 1, the master

reads from the slave device.

Data is sent over the serial bus in a sequence of nine clock

pulses, eight bits of data followed by an acknowledge bit from

the slave device. Transitions on the data line must occur during

the low period of the clock signal and remain stable during the

high period, since a low-to-high transition when the clock is

high may be interpreted as a stop signal. The number of data

bytes that can be transmitted over the serial bus in a single read

or write operation is limited only by what the master and slave

devices can handle.

When all data bytes have been read or written, stop conditions

are established. In write mode, the master will pull the data line

high during the tenth clock pulse to assert a stop condition. In

read mode, the master device will override the acknowledge bit

by pulling the data line high during the low period before the

ninth clock pulse. This is known as no acknowledge. The

master will then take the data line low during the low period

before the tenth clock pulse, then high during the tenth clock

pulse to assert a stop condition.

Any number of bytes of data may be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation. In the case of the ADT7481, write

operations contain either one or two bytes, while read

operations contain one byte.

To write data to one of the device data registers or to read data

from it, the address pointer register must be set so that the

correct data register is addressed. The first byte of a write

operation always contains a valid address that is stored in the

address pointer register. If data is to be written to the device, the

write operation contains a second data byte that is written to the

This procedure is illustrated in Figure 16. The device address is

sent over the bus followed by R/W set to 0 and followed by two

data bytes. The first data byte is the address of the internal data

internal data register.

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