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SLG46867MTR Datasheet(PDF) 63 Page - Renesas Technology Corp |
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SLG46867MTR Datasheet(HTML) 63 Page - Renesas Technology Corp |
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63 / 209 page ![]() Datasheet 28-Feb-2023 CFR0011-120-00 Revision 3.21 Page 63 of 208 © 2023 Renesas Electronics Corporation SLG46867 GreenPAK Programmable Mixed-Signal Matrix with Dual 44 m Ω/2 A P-FET 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT Figure 32: 4-bit LUT0 or DFF12 DFF12 CLK D 16-bits NVM 1-bit NVM 4-bit LUT0 OUT IN1 IN2 IN0 From Connection Matrix Output [52] From Connection Matrix Output [51] From Connection Matrix Output [50] registers [1439:1424] register [1414] To Connection Matrix Input [41] Q/nQ LUT Truth Table DFF/Latch Registers S0 S1 S0 S1 S0 S1 S0 S1 Q1/Q2 Select register [1436] IN3 From Connection Matrix Output [53] S0 S1 register [1439] DFF or LATCH Select register [1438] Output Select (Q or nQ) register [1437] DFF Initial Polarity Select register [1436] Q1 or Q2 Select register [1435] DFF nRST or nSET Select register [1434] Active level selection for RST/ SET nRST/nSET RST/SET Table 41: 4-bit LUT0 Truth Table IN3 IN2 IN1 IN0 OUT 0 0 0 0 register [1424] LSB 0 0 0 1 register [1425] 0 0 1 0 register [1426] 0 0 1 1 register [1427] 0 1 0 0 register [1428] 0 1 0 1 register [1429] 0 1 1 0 register [1430] 0 1 1 1 register [1431] 1 0 0 0 register [1432] 1 0 0 1 register [1433] 1 0 1 0 register [1434] 1 0 1 1 register [1435] 1 1 0 0 register [1436] 1 1 0 1 register [1437] 1 1 1 0 register [1438] 1 1 1 1 register [1439] MSB |
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