ADP3198 datasheet(12/32 Pages) AD

12 / 32 page

ADP3198

Rev. A | Page 12 of 32

To increase the current in any given phase, enlarge RSW for that

phase (make RSW = 0 for the hottest phase and do not change it

during balancing). Increasing RSW to only 500 Ω makes a

substantial increase in phase current. Increase each RSW value

by small amounts to achieve balance, starting with the coolest

phase first.

VOLTAGE CONTROL MODE

A high gain, high bandwidth, voltage mode error amplifier is

used for the voltage mode control loop. The control input

voltage to the positive input is set via the VID logic according to

the voltages listed in Table 4.

This voltage is also offset by the droop voltage for active

positioning of the output voltage as a function of current,

commonly known as active voltage positioning. The output

of the amplifier is the COMP pin, which sets the termination

voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with

Resistor RB and is used for sensing and controlling the output

voltage at this point. A current source (equal to IREF) from the

FB pin flowing through R

is used for setting the no load offset

voltage from the VID voltage. The no load voltage is negative

with respect to the VID DAC. The main loop compensation is

incorporated into the feedback network between FB and COMP.

CURRENT REFERENCE

The IREF pin is used to set an internal current reference. This

reference current sets IFB, IDELAY, ISS, ILIMIT, and ITTSENSE. A resistor

to ground programs the current based on the 1.5 V output.

IREF

Typically, RIREF is set to 100 kΩ to program IREF = 15 μA. The

following currents are then equal to

IFB

= IREF = 15 μA

IDELAY

= IREF = 15 μA

ISS

= IREF = 15 μA

ILIMIT

= 2/3 (IREF) = 10 μA

ENHANCED PWM MODE

Enhanced PWM mode is intended to improve the transient

response of the ADP3198 to a load setup. In previous

generations of controllers, when a load step up occurred, the

controller had to wait until the next turn-on of the PWM signal

to respond to the load change. Enhanced PWM mode allows

the controller to immediately respond when a load step up

occurs. This allows the phases to respond more quickly when a

load increase takes place.

DELAY TIMER

The delay times for the start-up timing sequence are set with

a capacitor from the DELAY pin to ground. In UVLO, or when

EN is logic low, the DELAY pin is held at ground. After the

UVLO and EN signals are asserted, the first delay time (TD1 in

Figure 7) is initiated. A current flows out of the DELAY pin to

charge CDLY. This current is equal to IREF, which is normally

15 μA. A comparator monitors the DELAY voltage with a

threshold of 1.7 V. The delay time is therefore set by the IREF

current charging a capacitor from 0 V to 1.7 V. This DELAY pin

is used for multiple delay timings (TD1, TD3, and TD5) during

the start-up sequence. In addition, DELAY is used for timing

the current-limit latch off, as explained in the Current-Limit,

Short-Circuit, and Latch-Off Protection section.

SOFT START

The soft start times for the output voltage are set with a

capacitor from the SS pin to ground. After TD1 and the phase

detection cycle are complete, the SS time (TD2 in Figure 7)

starts. The SS pin is disconnected from GND, and the capacitor

is charged up to the 1.1 V boot voltage by the SS amplifier,

which has an output current equal to IREF (normally 15 μA).

The voltage at the FB pin follows the ramping voltage on the

SS pin, limiting the inrush current during startup. The soft start

time depends on the value of the boot voltage and CSS.

Once the SS voltage is within 100 mV of the boot voltage, the

boot voltage delay time (TD3 in Figure 7) is started. The end of

the boot voltage delay time signals the beginning of the second

soft start time (TD4 in Figure 7). The SS voltage now changes

from the boot voltage to the programmed VID DAC voltage

(either higher or lower) using the SS amplifier with the output

current equal to IREF. The voltage of the FB pin follows the

ramping voltage of the SS pin, limiting the inrush current

during the transition from the boot voltage to the final DAC

voltage. The second soft start time depends on the boot voltage,

the programmed VID DAC voltage, and CSS.

ADP3198 Datasheet(PDF) 12 Page - Analog Devices

ADP3198 Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL