ADP3198 datasheet(14/32 Pages) AD

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ADP3198

Rev. A | Page 14 of 32

POWER-GOOD MONITORING

The power-good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open-drain output whose

high level, when connected to a pull-up resistor, indicates that

the output voltage is within the nominal limits specified based

on the VID voltage setting. PWRGD goes low if the output

voltage is outside of this specified range, if the VID DAC inputs

are in no CPU mode, or if the EN pin is pulled low. PWRGD is

blanked during a VID OTF event for a period of 200 μs to

prevent false signals during the time the output is changing.

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD5), based on the DELAY timer. Prior to the

SS voltage reaching the programmed VID DAC voltage and the

PWRGD masking-time finishing, the PWRGD pin is held low.

Once the SS pin is within 100 mV of the programmed DAC

voltage, the capacitor on the DELAY pin begins to charge.

A comparator monitors the DELAY voltage and enables

PWRGD when the voltage reaches 1.7 V. The PWRGD delay

time is set, therefore, by a current of IREF, charging a capacitor

from 0 V to 1.7 V.

OUTPUT CROWBAR

To protect the load and output components of the supply, the

PWM outputs are driven low, which turns on the low-side

MOSFETs when the output voltage exceeds the upper crowbar

threshold. This crowbar action stops once the output voltage

falls below the release threshold of approximately 375 mV.

Turning on the low-side MOSFETs pulls down the output as

the reverse current builds up in the inductors. If the output

overvoltage is due to a short in the high-side MOSFET, this

action current limits the input supply or blows its fuse,

protecting the microprocessor from being destroyed.

OUTPUT ENABLE AND UVLO

For the ADP3198 to begin switching, the input supply (VCC) to

the controller must be higher than the UVLO threshold and the

EN pin must be higher than its 0.85 V threshold. This initiates a

system start-up sequence. If either UVLO or EN is less than

their respective thresholds, the ADP3198 is disabled. This holds

the PWM outputs at ground, shorts the DELAY capacitor to

ground, and forces PWRGD and OD signals low.

In the application circuit (see Figure 10), the OD pin should be

connected to the OD inputs of the ADP3110A drivers.

Grounding OD disables the drivers such that both DRVH and

DRVL are grounded. This feature is important in preventing the

discharge of the output capacitors when the controller is shut

off. If the driver outputs are not disabled, a negative voltage can

be generated during output due to the high current discharge of

the output capacitors through the inductors.

THERMAL MONITORING

The ADP3198 includes a thermal-monitoring circuit to detect

when a point on the VR has exceeded two different user-

defined temperatures. The thermal-monitoring circuit requires

an NTC thermistor to be placed between TTSENSE and GND.

A fixed current of 8 × IREF (normally giving 123 μA) is sourced

out of the TTSENSE pin and into the thermistor. The current

source is internally limited to 5 V. An internal circuit compares

the TTSENSE voltage to a 1.105 V and a 0.81 V threshold, and

outputs an open-drain signal at the VRFAN and VRHOT

outputs, respectively. Once the voltage on the TTSENSE pin

drops below its respective threshold, the open-drain outputs

assert high to signal the system that an overtemperature event

has occurred. Because the TTSENSE voltage changes slowly

with respect to time, 50 mV of hysteresis is built into these com-

parators. The thermal monitoring circuitry does not depend on

EN and is active when UVLO is above its threshold. When UVLO

is below its threshold, VRFAN and VRHOT are forced low.

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