ADP3198 datasheet(26/32 Pages) AD

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ADP3198

Rev. A | Page 26 of 32

Solving for the power dissipation per MOSFET at IO = 119 A and

IR = 11 A yields 958 mW for each synchronous MOSFET and

872 mW for each main MOSFET. A guideline to follow is to limit

the MOSFET power dissipation to 1 W. The values calculated in

Equation 25 and Equation 26 comply with this guideline.

Finally, consider the power dissipation in the driver for each

phase. This is best expressed as QG for the MOSFETs and is

given by Equation 27, where QGMF is the total gate charge for

each main MOSFET and QGSF is the total gate charge for each

synchronous MOSFET.

()

GSF

GMF

DRV

⎥

⎦

⎤

⎢

⎣

⎡

(27)

Also shown is the standby dissipation factor (ICC × VCC) of the

driver. For the ADP3110A, the maximum dissipation should be less

than 400 mW. In this example, with ICC = 7 mA, QGMF = 5.8 nC,

and QGSF = 48 nC, there is 297 mW in each driver, which is

below the 400 mW dissipation limit. See the ADP3110A data

sheet for more details.

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the best

combination of thermal balance, stability, and transient response.

Equation 28 is used for determining the optimum value.

kΩ

356

2.4

320

0.2

(28)

where:

AR is the internal ramp amplifier gain.

AD is the current balancing amplifier gain.

RDS is the total low-side MOSFET on resistance.

CR is the internal ramp capacitor value.

The internal ramp voltage magnitude can be calculated by using

()

kHz

330

357

1.3

0.108

0.2

−

VID

(29)

The size of the internal ramp can be made larger or smaller.

If it is made larger, stability and noise rejection improves, but

transient degrades. Likewise, if the ramp is made smaller,

transient response improves at the sacrifice of noise rejection

and stability.

The factor of 3 in the denominator of Equation 28 sets a ramp

size that gives an optimal balance for good stability, transient

response, and thermal balance.

COMP PIN RAMP

A ramp signal on the COMP pin is due to the droop voltage

and output voltage ramps. This ramp amplitude adds to the

internal ramp to produce the following overall ramp signal

at the PWM input:

()

⎟

⎠

⎞

⎜

⎝

⎛

−

(30)

In this example, the overall ramp signal is 0.46 V. However,

if the ramp size is smaller than 0.5 V, increase the ramp size

to be at least 0.5 V by decreasing the ramp resistor for noise

immunity. Because there is only 0.46 V initially, a ramp resistor

value of 332 kΩ is chosen for this example, yielding an overall

ramp of 0.51 V.

CURRENT-LIMIT SETPOINT

To select the current-limit setpoint, first find the resistor value

for RLIM. The current-limit threshold for the ADP3198 is set

with a constant current source flowing out of the ILIMIT pin,

which sets up a voltage (VLIM) across RLIM with a gain of

82.6 mV/V (ALIM). Thus, increasing RLIM now increases the

current limit. RLIM can be found using

REF

CSA

LIM

ILIMIT

LIM

(31)

Here, ILIM is the peak average current limit for the supply output.

The peak average current is the dc current limit plus the output

ripple current. In this example, choosing a dc current limit of

159 A and having a ripple current of 11 A gives an ILIM of 170 A.

This results in an RLIM = 205.8 kΩ, for which 205 kΩ is chosen

as the nearest 1% value.

The per-phase initial duty cycle limit and peak current during a

load step are determined by

()

BIAS

MAX

COMP

MAX

−

(32)

(

)

VID

MAX

PHMAX

−

≅

(33)

For the ADP3198, the maximum COMP voltage (VCOMP(MAX))

is 4.0 V and the COMP pin bias voltage (VBIAS) is 1.1 V. In this

example, the maximum duty cycle is 0.61 and the peak current

is 62 A.

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