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MPC8347A Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc

Part # MPC8347A
Description  Integrated Host Processor Hardware Specifications
PDF  108 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8347A Datasheet(HTML) 35 Page - Freescale Semiconductor, Inc

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
35
8.3.2
MII Management AC Electrical Specifications
Table 33 provides the MII management AC timing specifications.
Figure 15 shows the MII management AC timing diagram.
Figure 15. MII Management Interface Timing Diagram
Table 33. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V ± 10% or 2.5 V ± 5%
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—2.5
—
MHz
2
MDC period
tMDC
—400
—
ns
MDC clock pulse width high
tMDCH
32
—
—
ns
MDC to MDIO delay
tMDKHDX
10
—
170
ns
3
MDIO to MDC setup time
tMDDVKH
5—
—
ns
MDIO to MDC hold time
tMDDXKH
0—
—
ns
MDC rise time
tMDCR
——
10
ns
MDC fall time
tMDHF
——
10
ns
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data
outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with
respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going
to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency
is 8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is
11.7 MHz and the minimum frequency is 1.7 MHz).
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for
a csb_clk of 333 MHz, the delay is 58 ns).
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
MDIO
(Input)
(Output)



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