MPC8347A datasheet(82/108 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

LVDD1

U20, W25

Power for

Three Speed

Ethernet #1

and for

Ethernet

Management

Interface I/O

(2.5V, 3.3V)

LVDD1

LVDD2

V20, Y23

Power for

Three Speed

Ethernet #2

I/O (2.5V,

3.3V)

LVDD2

VDD

J11, J12, J15, K10, K11, K12, K13, K14,

K15, K16, K17, K18, K19, L10, L11, L18,

L19, M10, M19, N10, N19, P9, P10, P19,

R10, R19, R20, T10, T19, U10, U19, V10,

V11, V18, V19, W11, W12, W13, W14, W15,

W16, W17, W18

Power for

Core

(1.2 V)

VDD

OVDD

B27, D3, D11, D19, E15, E23, F5, F8, F11,

F14, F17, F20, G24, H23, H24, J6, J14, J17,

J18, K4, L9, L20, L23, L25, M6, M9, M20,

P5, P20, P23, R6, R9, R24, U23, V4, V6

PCI, 10/100

Ethernet, and

other

Standard

(3.3 V)

OVDD

MVREF1

AF19

DDR

Reference

Voltage

MVREF2

AE10

DDR

Reference

Voltage

No Connection

V1, V2, V5

Notes:

1. This pin is an open-drain signal. A weak pull-up resistor (1 k

Ω) should be placed on this pin to OV

2. This pin is an open-drain signal. A weak pull-up resistor (2–10 k

Ω) should be placed on this pin to OV

DD.

3. During reset, this output is actively driven rather than three-stated.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.

6. .This pin must always be tied to GND

7. This pin must always be left not connected

8. Thermal sensitive resistor.

9. It is recommended that MDIC0 be tied to GRD using an 18

Ω resistor and MDIC1 be tied to DDR power using an 18 Ω

resistor.

Table 55. MPC8347EA (PBGA) Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

MPC8347A Datasheet(PDF) 82 Page - Freescale Semiconductor, Inc

MPC8347A Datasheet(HTML) 82 Page - Freescale Semiconductor, Inc

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