| Electronic Components Datasheet Search |
|
MPC8347A Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8347A Datasheet(HTML) 16 Page - Freescale Semiconductor, Inc |
|
16 / 108 page ![]() MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 16 Freescale Semiconductor DDR and DDR2 SDRAM 6 DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8347EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V. The AC electrical specifications are the same for DDR and DRR2 SDRAM. NOTE The information in this document is accurate for revision 3.0 silicon and later. For information on revision 1.1 silicon and earlier versions see the MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications. See Section 23.1, “Part Numbers Fully Addressed by this Document,” for silicon revision level determination. 6.1 DDR and DDR2 SDRAM DC Electrical Characteristics Table 11 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8347EA when GVDD(typ) = 1.8 V. Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V Parameter/Condition Symbol Min Max Unit Notes I/O supply voltage GVDD 1.71 1.89 V 1 I/O reference voltage MVREF 0.49 × GV DD 0.51 × GV DD V2 I/O termination voltage VTT MVREF –0.04 MVREF + 0.04 V 3 Input high voltage VIH MVREF+0.125 GVDD +0.3 V Input low voltage VIL –0.3 MVREF – 0.125 V Output leakage current IOZ –9.9 9.9 μA4 Output high current (VOUT = 1.420 V) IOH –13.4 — mA Output low current (VOUT = 0.280 V) IOL 13.4 — mA Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF cannot exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ V OUT ≤ GVDD. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |