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NVT2002TLH Datasheet(PDF) 3 Page - NXP Semiconductors |
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NVT2002TLH Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 32 page  NXP Semiconductors NVT2001; NVT2002 Bidirectional voltage level translator for open-drain and push-pull applications 4 Functional diagram 002aae132 A1 An VREFA GND VREFB B1 Bn EN SW SW NVT20xx Figure 1. Logic diagram of NVT2001; NVT2002 (positive logic) 5 Pinning information 5.1 Pinning 5.1.1 1-bit in XSON6 package NVT2001GM VREFA 002aae211 GND A1 VREFB EN B1 Transparent top view 2 3 1 5 4 6 Figure 2. Pin configuration for XSON6 5.1.2 2-bit in TSSOP8 and XSON8U packages NVT2002DP GND EN VREFA VREFB A1 B1 A2 B2 002aae214 1 2 3 4 6 5 8 7 Figure 3. Pin configuration for TSSOP8 002aae215 NVT2002GD Transparent top view 8 7 6 5 1 2 3 4 GND VREFA A1 A2 EN VREFB B1 B2 Figure 4. Pin configuration for XSON8U NVT2001_NVT2002 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 4.4 — 22 May 2023 3 / 32 |
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